Download Digital Circuits for Data Storage and Transmission: Understanding Shift Registers and more Assignments Computer Vision in PDF only on Docsity!
UNIT- 5
Registers: A Register is a digital circuit that both stores data and moves data. Shift Register: Shift registers are a type of sequential logic circuit, mainly for storage of digital data. They are a group of flip-flops connected in a chain so that the output from one flip-flop becomes the input of the next flip-flop. Most of the registers possess no characteristic internal sequence of states. All flip-flop is driven by a common clock, and all are set or reset simultaneously. Buffer Register: Buffer registers are a type of registers used to store a binary word. These can be constructed using a series of flip-flops as each flip-flop can store a single bit. This means that in order to store an n-bit binary word one should design an array of n flip-flops. Figure 1 shows a 4 bit synchronous buffer register formed by cascading four positive edge triggered D flip-flops. Here the entire input data word B1B2B3B4 is loaded onto the register at a single clock tick. This means that at every leading edge of the clock the values of flip-flop outputs follow their input bits i.e. Q1 = B1, Q2 = B2, Q3 = B3 and Q4 = B4 as shown by Figure 2. Buffer registers offer no means of control over the inputs which in turn leads to uncontrolled outputs. In order to overcome this drawback one can resort to controlled buffer registers as shown by Figure 3. In this design, tri-state switches are used to control the operation of loading and/or retrieval of the data to/from the buffer register. Here one has to pull the or Control line(blue line) low in order to store the data into the register, while Control line(red line) should be made low to read the data.
Data transmission in shift register: The binary data in a register can be moved within the register from one flip-flop to another. The registers that allow such data transfers are called as shift registers. There are four mode of operations of a shift register.
- Serial Input Serial Output
- Serial Input Parallel Output
- Parallel Input Serial Output
- Parallel Input Parallel Output
Serial Input Serial Output
Let all the flip-flop be initially in the reset condition i.e. Q3 = Q2 = Q1 = Q0 = 0. If an entry of a four bit binary number 1 1 1 1 is made into the register, this number should be applied to Din bit with the LSB bit applied first. The D input of FF-3 i.e. D3 is connected to serial data input Din. Output of FF-3 i.e. Q3 is connected to the input of the next flip-flop i.e. D2 and so on.
Block Diagram
Operation
Before application of clock signal, let Q3 Q2 Q1 Q0 = 0000 and apply LSB bit of the number to be entered to Din. So Din = D3 = 1. Apply the clock. On the first
Truth Table
Waveforms
Serial Input Parallel Output
- In such types of operations, the data is entered serially and taken out in parallel fashion.
- Data is loaded bit by bit. The outputs are disabled as long as the data is loading.
- As soon as the data loading gets completed, all the flip-flops contain their required data, the outputs are enabled so that all the loaded data is made available over all the output lines at the same time.
- 4 clock cycles are required to load a four bit word. Hence the speed of operation of SIPO mode is same as that of SISO mode.
Block Diagram
Parallel Input Parallel Output (PIPO)
In this mode, the 4 bit binary input B0, B1, B2, B3 is applied to the data inputs D0, D1, D2, D3 respectively of the four flip-flops. As soon as a negative clock edge is applied, the input binary bits will be loaded into the flip-flops simultaneously. The loaded bits will appear simultaneously to the output side. Only clock pulse is essential to load all the bits.
Block Diagram
Bidirectional Shift Register
- If a binary number is shifted left by one position then it is equivalent to multiplying the original number by 2. Similarly if a binary number is shifted right by one position then it is equivalent to dividing the original number by 2.
- Hence if we want to use the shift register to multiply and divide the given binary number, then we should be able to move the data in either left or right direction.
- Such a register is called bi-directional register. A four bit bi-directional shift register is shown in fig.
- There are two serial inputs namely the serial right shift data input DR, and the serial left shift data input DL along with a mode select input (M).
Block Diagram
Universal Shift Register A shift register which can shift the data in only one direction is called a uni- directional shift register. A shift register which can shift the data in both directions is called a bi-directional shift register. Applying the same logic, a shift register which can shift the data in both directions as well as load it parallely, is known as a universal shift register. The shift register is capable of performing the following operation −
- Parallel loading
- Left Shifting
- Right shifting The mode control input is connected to logic 1 for parallel loading operation whereas it is connected to 0 for serial shifting. With mode control pin connected to ground, the universal shift register acts as a bi-directional register. For serial left operation, the input is applied to the serial input which goes to AND gate-1 shown in figure. Whereas for the shift right operation, the serial input is applied to D input.
Block Diagram
Counters: Counter is a sequential circuit. A digital circuit which is used for a counting pulses is known counter. Counter is the widest application of flip-flops. It is a group of flip-flops with a clock signal applied.
Classification:
Counters are of two types.
- Asynchronous or ripple counters.
- Synchronous counters.
Asynchronous or ripple counters:
The input signal is applied to the clock input of the first FF, and the output of each FF is connected directly to the clock input of the next. The logic diagram of a 2-bit ripple up counter is shown in figure. The toggle (T) flip-flop are being used. But we can use the JK flip-flop also with J and K connected permanently to logic 1. External clock is applied to the clock input of flip-flop A and QA output is applied to the clock input of the next flip-flop i.e. FF- B.
Logical Diagram
Operation
S.N. Condition Operation 1 Initially let both the FFs be in the reset state QBQA = 00 initially 2 After 1st negative clock edge As soon as the first negative clock edge is applied, FF-A will toggle and QA will be equal to 1. QA is connected to clock input of FF-B. Since QA has changed from 0 to 1, it is treated as the positive clock edge by FF-B. There is no change in QB because FF-B is a negative
Effect of propagation delay in ripple counters: A major problem with ripple counters arises from the propagation delay of the flip-flops constituting the counter. The effective propagation delay in a ripple counter is equal to the sum of propagation delays due to different flip-flops. The situation becomes worse with increase in the number of flip-flops used to construct the counter, which is the case in larger bit counters. An increased propagation delay puts a limit on the maximum frequency used as clock input to the counter. We can appreciate that the clock signal time period must be equal to or greater than the total propagation delay. The maximum clock frequency therefore corresponds to a time period that equals the total propagation delay. If tpd is the propagation delay in each flip-flop, then, in a counter with N flip-flops having a modulus of less than or equal to 2N , the maximum usable clock frequency is given by fmax = 1/(N × tpd). Often the propagation delay times are specified in the case of flip-flops, one for LOW-to- HIGH transition (tpLH) and the other for HIGH-to-LOW transition (tpHL) at the output. In such a case, the larger of the two should be considered for computing the maximum clock frequency.
