RAKESH ASERY
Experiment No:-[4a]
Aim: - To Design D Flip-flop using Verilog and simulate the same using Xilinx ISE
Simulator.
TOOLS REQUIRED: - PC, Xilinx ISE.
THEORY: -
It is also known as a "data" or "delay" flip-flop. The D flip-flop captures the value of the D-input
at a definite portion of the clock cycle (such as the rising edge of the clock). That captured value
becomes the Q output. At other times, the output Q does not change. The D flip-flop can be
viewed as a memory cell, a zero-order hold, or a delay line.
If clock=1 then Output Q=D.
VERILOG CODE
BEHAVIOURAL: -
module RAKSHKDFF(Q, CLK, D);
output Q,CLK,D;
reg Q;
initial Q=0;
always@(CLK or D)
if(CLK)
