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Test Sloppily -Components and Design Techniques for Digital System - Exams, Exams of Digital Systems Design

Main points of this past exam are: Test Sloppily, Partial Credit, Rom Contents, Unethical Actions, Cost Money, Hexadecimal, Assigned Numerical, Numerical Order, Follow Normal, State Diagram

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UNIVERSITY OF CALIFORNIA
College of Engineering
Department of Electrical Engineering
and Computer Sciences
Professor Fearing Fall 1999
EECS 150 – QUIZ #2
Tuesday, 4 November 1998, 2:10-3:30 p.m.
Name: _________________________________ ID#: ____________
Closed book. No notes. No calculators.
There are 4 problems worth 100 points total. There is little room for partial credit—it’s better to do half the
test carefully than to do the entire test sloppily.
In the real world, unethical actions by engineers can cost money, careers, and lives. The penalty for unethical
actions on this exam will be a grade of zero.
Problem Points Your Score
1 16
2 20
3 50
4 14
Total 100
1 of 7
Problem 1 (16 points)
List the ROM contents in hexadecimal to impl ement the FSM shown below. The inp uts A and B are synchro-
nized. The states are assigned numerical order, e.g., for state S4, Q2Q1Q0 = 1002. (Follow normal state diagram
assumptions: holding in the same state is implicit, etc.).
Fill in ROM contents in hexadecimal. (Binary answers will receive no credit.)
Address Data
0
1
2
3
4
5
6
7
Address Data
8
9
A
B
C
D
E
F
Address Data
10
11
12
13
14
15
16
17
Address Data
18
19
1A
1B
1C
1D
1E
1F
000 001 010 011
100 101 110 111
A0
AB 1
AB 0A0
A1
AB 1
AB 1
AB 1
AB 0
AB 0
A1A1
AB 0
AB 0
AB 1
AB 0
AB 0
AB 1
AB 1
AB 1A0
AB 0
AB 0
A1
AB 1
AB 0
A0
A1
A2
A3
A4
O0
O1
O2
D0
D1
D2 Q2
Q1
Q0
Q2
Q1
Q0
A
BQ2
Q0
Q1
OUT
RESET (synchronous)
CLOCK
RESET
ROM
32×4
O3
pf2

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UNIVERSITY OF CALIFORNIA

College of Engineering

Department of Electrical Engineering

and Computer Sciences

Professor Fearing

Fall 1999

EECS 150 – QUIZ

Tuesday, 4 November 1998, 2:10-3:30 p.m.

Name:

_________________________________

ID#: ____________

Closed book. No notes. No calculators.

There are 4 problems worth 100 points total. There is little room for partial credit—it’s better to do half thetest carefully than to do the entire test sloppily.

In the real world, unethical actions by engineers can cost money, careers, and lives. The penalty for unethical

actions on this exam will be a grade of zero.

Problem

Points

Your Score

Total

of

Problem 1

(16 points)

List the ROM contents in

hexadecimal

to implement the FSM shown below. The inputs A and B are synchro-

nized. The states are assigned numerical order, e.g., for state S4, Q

Q

Q

. (Follow normal state diagram

assumptions: holding in the same state is implicit, etc.).Fill in ROM contents in hexadecimal. (Binary answers will receive no credit.)

Address

Data

Address

Data

8 9 ABCDEF

Address

Data

Address

Data

1819 1A1B1C1D1E1F

A

0

AB

1

AB

0

A

0

A

1

AB

1

AB

1

AB

1

AB

0

AB

0

A

1

A

1

AB

0

AB

0

AB

1

AB

0

AB

0

AB

1

AB

1

AB

1

A

0

AB

0

AB

0

A

1

AB

1

AB

0

A4A3A2A1 A

O

O

O

D2D1D

Q2Q1Q

Q2Q1Q

AB

Q2Q1Q

OUT

RESET (synchronous) CLOCK

RESET

ROM 32

×

O

of

Problem 2

(20 points)

Your lab partner has designed the following Xilinx XC4000 circuit and tells you it works fine in unit delay simu-lation, but won’t work when downloaded to the Xilinx chip. Given CLKIN=1MHz, T

ckomax

=2.8ns, T

su

=2.4ns.

[12 pts.] a)

Complete the timing diagram (considering propagation and interconnect delays) to show why thecircuit does not operate as intended.

[4 pts.]

b)

Circle the problem area(s) in the timing diagram, and briefly explain in a full sentence what theproblem is.

[4 pts.]

c)

Modify the design above so it will work as intended. Do not add any gates or FF.

CLK

FDRE

Q

0

CLKIN

BUFGS

IBUF

IPAD

CLK

D

Q

CE

R

CLK

D

Q

CE

R

D

Q

1

Q

0

Q

1

FDRE

D

Q

BUFGS

CLK

FD

CLK

CLK

CLK

D0 Q

Q

of

Problem 3

(50 points)

You are given the 8-bit data path below. The SRAM is

, but has the same operating characteristics as the

static RAM used in lab. 8-bit binary counter CB8RE has synchronous reset.

×

Clock

R CE

Q(7:0)

TC

CNT0TC

CLR0CNT

COUNTER

MUX

CNTSEL

Clock R CE

Q(7:0)

TC

CNT1TC

CLR

CNT

COUNTER

CB8RE CB8RE

×

SRAM

ADDRESS

DATA

CE.L

OE.L

WE.L

Q

D

Clock

Q

D

Clock

OE-FE

WE-FE

Clock

D

Q

CE

A

LOADA

ENA

Databus<7:0>

ADRBUS<7:0>

BUFE

WECE OE