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Problem 1
FSM Design Problem (15 points)
- In this problem, you will design an FSM which takes a synchronized serial input IN (presented LSB first) andoutputs a serial bit stream OUT which represents the input plus 3. For example, if the input were
the
output stream would be
. (Note that there is an output bit for every input bit. In the idle state on RESET,
a zero is output.) Hint: the state machine needs to keep track of the carry bit. [8 pts.]^
a)^ Complete the state diagram for a Moore type FSM. Be sure to specify labels on transitions, and out-puts. [7 pts.]
b)^ Complete the state table for the Moore FSM which implements the plus 3 function.
11012 IDLE
S^1
S^6
S^5
S^4
S^3
S^2
S^0 OUT=
RESET
IN^ IN
InputIN
PresentState
NextState
OutputOUT
0 1
S 0 1
S 0 1
S 0 1
S 0 1
S 0 1
S 0 1
S
Problem 2
FSM Design Problem (10 points) Design a Moore FSM which outputs a single high pulse of width one clock cycle every time the synchronizedinput signal START changes from 0 to 1. [7 pts.]
a)^ Show state diagram: [3 pts.]
b)^ Show schematic for this FSM using type D FF(s) and minimal extra gates.
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Problem 3
FSM/Microprogram Analysis (20 points) [12 pts.] a)
Complete the timing diagram for the computer data path and control unit shown on the next page.All components are synchronous. The microprogram ROM contents in Hexadecimal are: [2 pts.]
b)^ Label the timing diagram with the micro program address. [6 pts.]
c)^ List, in register transfer notation, the data transfer occurring at and after the noted clock edge.
Address
Hex Data
Address
Hex Data
0
38
4
EO
1
32
5
EO
2
06
6
EO
3
34
7
EO
Clock
× Clock READ WRITE CS.L WE.L DataBusACLOADmicro programaddressRESET
HiZ^ RAM [MAR]
A^^0
B^
C^
D
HiZ^ A: 0^
Õ^ PC, 0
Õ^ μPC C:^ ______________________
B:^ ______________________ D:^ ______________________
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[5 pts.]
b)^ List signals which come from the data path and are input to the controller:List control signals generated by the controlled which control the data path. [10 pts.] c)
Draw a timing diagram which shows all the relevant control signals necessary for reading in the first4 code words, storing in RAM, and updating the RAM address. Assume that control signals are gen-erated by a Moore type FSM running at 4 MHz. Show as many signals as necessary. Assume thesystem has already received 16 bits. Clock SerialDataCS.L WE.L
Problem 6
Short Answer Section (20 points) [2 pts.]
a)^ Can metastability be completely eliminated in real digital systems with external inputs? If yes, howcan metastability be eliminated? If no, what can be done to minimize problems? [2 pts.]
b)^ You observe that an FSM with 100ns clock period and 1MHz asynchronous input (which is syn-chronized by a D type-edge triggered FF) fails to go to the correct next state on average once persecond. The Xilinx timing analyzer tells you that the minimum clock period is 97 ns for the circuit.When you change the clock period to 110 ns, the error disappears. What is a possible cause for theFSM faulty next state? [2 pts.]
c)^ You have been asked to design a certain digital system for a portable multimedia application. Themarketing department tells you to make a case for using either digital hardware or a general purposeCPU and software to implement certain algorithms.List 3 reasons why the digital hardware (e.g., Xilinx or custom VLSI chip) approach might be better:1) 2) 3) List 3 reasons why the general purpose CPU and software approach might be better:1)2) 3) [1 pts.]
d)^ Explain what a tri-state device is (what are the three states)? When are tristate devices useful? [3 pts.]
e)^ Find the minimal sum-of-products form for
[2 pts.]
f)^ A system has two Xilinx boards. On each board, the output of the Xilinx chip is clean, when youconnect these outputs through a 0.5m cable to another Xilinx board, now there are glitches on thesignal and clock lines. Suggest a likely cause of the glitches.
Y^ ACD
ABC
BCD
ABD
ABCD
+^
+^
+^
[3 pts.]
g)^ You are working with a Xilinx board which works perfectly with theTA .bit file. Your design simu-lates without a problem using ViewSim. Your .bit file configures the Xilinx correctly, but yourdesign does not function.1)
What is the most likely cause of the problem?2) Suggest a plan for finding, then fixing the problem? [2 pts.]
h)^ A student project has two communicating Mealey machines connected, as shown below. What is thebiggest potential problem with this design? Show how by simply changing some connections theproblem will go away. [3 pts.]
i)^ State minimization. For the following state table, determine which states are equivalent.
Present state
INPUT
Output
Next state
S0S
01
11
S1S
S1S
0 1
0 0
S2S
S2S
0 1
1 1
S3S
S3S
01
00
Clock^ Clock S0S
to data path andother FSM
Outputdecoder D^ Q nextstatedecoder
inputs from data pathand other FSM
to data path andother FSM
Outputdecoder D^ Q nextstatedecoder
inputs from data pathand other FSM
