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SOLUTIONS MANUAL

OPERATING SYSTEMS:

INTERNALS AND DESIGN PRINCIPLES

SIXTH EDITION

WILLIAM STALLINGS

Copyright 2008: William Stallings

© 2008 by William Stallings

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TABLE OF CONTENTS

• Chapter 1 Computer System Overview...............................................................
• Chapter 2 Operating System Overview.............................................................
• Chapter 3 Process Description and Control......................................................
• Chapter 4 Threads, SMP and Microkernels
• Chapter 5 Concurrency: Mutual Exclusion and Synchronization
• Chapter 6 Concurrency: Deadlock and Starvation
• Chapter 7 Memory Management
• Chapter 8 Virtual Memory
• Chapter 9 Uniprocessor Scheduling...................................................................
• Chapter 10 Multiprocessor and Real-Time Scheduling
• Chapter 11 I/O Management and Disk Scheduling
• Chapter 12 File Management
• Chapter 13 Embedded Operating Systems
• Chapter 14 Computer Security Threats
• Chapter 15 Computer Security Techniques
• Chapter 16 Distributed Processing, Client/Server, and Clusters................
• Chapter 17 Networking
• Chapter 18 Distributed Process Management
• Appendix A Topics in Concurrency

CHAPTER 1 COMPUTER SYSTEM OVERVIEW

A A N S W E R S T ON S W E R S T O QQ U E S T I O N SU E S T I O N S

1.1 A main memory , which stores both data and instructions: an arithmetic and logic unit (ALU) capable of operating on binary data; a control unit , which interprets the instructions in memory and causes them to be executed; and input and output (I/O) equipment operated by the control unit. 1.2 User-visible registers: Enable the machine- or assembly-language programmer to minimize main memory references by optimizing register use. For high-level languages, an optimizing compiler will attempt to make intelligent choices of which variables to assign to registers and which to main memory locations. Some high- level languages, such as C, allow the programmer to suggest to the compiler which variables should be held in registers. Control and status registers: Used by the processor to control the operation of the processor and by privileged, operating system routines to control the execution of programs. 1.3 These actions fall into four categories: Processor-memory: Data may be transferred from processor to memory or from memory to processor. Processor-I/O: Data may be transferred to or from a peripheral device by transferring between the processor and an I/O module. Data processing: The processor may perform some arithmetic or logic operation on data. Control: An instruction may specify that the sequence of execution be altered. 1.4 An interrupt is a mechanism by which other modules (I/O, memory) may interrupt the normal sequencing of the processor. 1.5 Two approaches can be taken to dealing with multiple interrupts. The first is to disable interrupts while an interrupt is being processed. A second approach is to define priorities for interrupts and to allow an interrupt of higher priority to cause a lower-priority interrupt handler to be interrupted. 1.6 The three key characteristics of memory are cost, capacity, and access time. 1.7 Cache memory is a memory that is smaller and faster than main memory and that is interposed between the processor and main memory. The cache acts as a buffer for recently used memory locations. 1.8 Programmed I/O: The processor issues an I/O command, on behalf of a process, to an I/O module; that process then busy-waits for the operation to be completed before proceeding. Interrupt-driven I/O: The processor issues an I/O command on behalf of a process, continues to execute subsequent instructions, and is interrupted

1.3 a. 224 = 16 MBytes b. (1) If the local address bus is 32 bits, the whole address can be transferred at once and decoded in memory. However, since the data bus is only 16 bits, it will require 2 cycles to fetch a 32-bit instruction or operand. (2) The 16 bits of the address placed on the address bus can't access the whole memory. Thus a more complex memory interface control is needed to latch the first part of the address and then the second part (since the microprocessor will end in two steps). For a 32-bit address, one may assume the first half will decode to access a "row" in memory, while the second half is sent later to access a "column" in memory. In addition to the two-step address operation, the microprocessor will need 2 cycles to fetch the 32 bit instruction/operand. c. The program counter must be at least 24 bits. Typically, a 32-bit microprocessor will have a 32-bit external address bus and a 32-bit program counter, unless on- chip segment registers are used that may work with a smaller program counter. If the instruction register is to contain the whole instruction, it will have to be 32 - bits long; if it will contain only the op code (called the op code register) then it will have to be 8 bits long. 1.4 In cases (a) and (b) , the microprocessor will be able to access 2^16 = 64K bytes; the only difference is that with an 8-bit memory each access will transfer a byte, while with a 16-bit memory an access may transfer a byte or a 16-byte word. For case (c) , separate input and output instructions are needed, whose execution will generate separate "I/O signals" (different from the "memory signals" generated with the execution of memory-type instructions); at a minimum, one additional output pin will be required to carry this new signal. For case (d) , it can support 2^8 = 256 input and 2^8 = 256 output byte ports and the same number of input and output 16-bit ports; in either case, the distinction between an input and an output port is defined by the different signal that the executed input or output instruction generated. 1.5 Clock cycle =

8 MHz = 125 ns Bus cycle = 4 × 125 ns = 500 ns 2 bytes transferred every 500 ns; thus transfer rate = 4 MBytes/sec Doubling the frequency may mean adopting a new chip manufacturing technology (assuming each instructions will have the same number of clock cycles); doubling the external data bus means wider (maybe newer) on-chip data bus drivers/latches and modifications to the bus control logic. In the first case, the speed of the memory chips will also need to double (roughly) not to slow down the microprocessor; in the second case, the "word length" of the memory will have to double to be able to send/receive 32-bit quantities. 1.6 a. Input from the Teletype is stored in INPR. The INPR will only accept data from the Teletype when FGI=0. When data arrives, it is stored in INPR, and FGI is set to 1. The CPU periodically checks FGI. If FGI =1, the CPU transfers the contents of INPR to the AC and sets FGI to 0. When the CPU has data to send to the Teletype, it checks FGO. If FGO = 0, the CPU must wait. If FGO = 1, the CPU transfers the contents of the AC to OUTR and sets FGO to 0. The Teletype sets FGI to 1 after the word is printed.

b. The process described in (a) is very wasteful. The CPU, which is much faster than the Teletype, must repeatedly check FGI and FGO. If interrupts are used, the Teletype can issue an interrupt to the CPU whenever it is ready to accept or send data. The IEN register can be set by the CPU (under programmer control) 1.7 If a processor is held up in attempting to read or write memory, usually no damage occurs except a slight loss of time. However, a DMA transfer may be to or from a device that is receiving or sending data in a stream (e.g., disk or tape), and cannot be stopped. Thus, if the DMA module is held up (denied continuing access to main memory), data will be lost. 1.8 Let us ignore data read/write operations and assume the processor only fetches instructions. Then the processor needs access to main memory once every microsecond. The DMA module is transferring characters at a rate of 1200 characters per second, or one every 833 μs. The DMA therefore "steals" every 833rd cycle. This slows down the processor approximately

× 100% = 0.12%

1.9 a. The processor can only devote 5% of its time to I/O. Thus the maximum I/O instruction execution rate is 10^6 × 0.05 = 50,000 instructions per second. The I/O transfer rate is therefore 25,000 words/second. b. The number of machine cycles available for DMA control is 106 (0.05 × 5 + 0.95 × 2) = 2.15 × 106 If we assume that the DMA module can use all of these cycles, and ignore any setup or status-checking time, then this value is the maximum I/O transfer rate. 1.10 a. A reference to the first instruction is immediately followed by a reference to the second. b. The ten accesses to a[i] within the inner for loop which occur within a short interval of time. 1.11 Define Ci = Average cost per bit, memory level i Si = Size of memory level i Ti = Time to access a word in memory level i Hi = Probability that a word is in memory i and in no higher-level memory Bi = Time to transfer a block of data from memory level (i + 1) to memory level i Let cache be memory level 1; main memory, memory level 2; and so on, for a total of N levels of memory. Then Cs = Ci Si i = 1 N ∑ Si i = 1 N ∑

1.13 There are three cases to consider: Location of referenced word Probability Total time for access in ns In cache 0.9 20 Not in cache, but in main memory

Not in cache or main memory (0.1)(0.4) = 0.04 12ms + 60 + 20 = 12,000, So the average access time would be: Avg = (0.9)(20) + (0.06)(80) + (0.04)(12000080) = 480026 ns 1.14 Yes, if the stack is only used to hold the return address. If the stack is also used to pass parameters, then the scheme will work only if it is the control unit that removes parameters, rather than machine instructions. In the latter case, the processor would need both a parameter and the PC on top of the stack at the same time.

CHAPTER 2 OPERATING SYSTEM OVERVIEW

A A N S W E R S T ON S W E R S T O QQ U E S T I O N SU E S T I O N S

2.1 Convenience: An operating system makes a computer more convenient to use. Efficiency: An operating system allows the computer system resources to be used in an efficient manner. Ability to evolve: An operating system should be constructed in such a way as to permit the effective development, testing, and introduction of new system functions without interfering with service. 2.2 The kernel is a portion of the operating system that includes the most heavily used portions of software. Generally, the kernel is maintained permanently in main memory. The kernel runs in a privileged mode and responds to calls from processes and interrupts from devices. 2.3 Multiprogramming is a mode of operation that provides for the interleaved execution of two or more computer programs by a single processor. 2.4 A process is a program in execution. A process is controlled and scheduled by the operating system. 2.5 The execution context, or process state, is the internal data by which the operating system is able to supervise and control the process. This internal information is separated from the process, because the operating system has information not permitted to the process. The context includes all of the information that the operating system needs to manage the process and that the processor needs to execute the process properly. The context includes the contents of the various processor registers, such as the program counter and data registers. It also includes information of use to the operating system, such as the priority of the process and whether the process is waiting for the completion of a particular I/O event. 2.6 Process isolation: The operating system must prevent independent processes from interfering with each other's memory, both data and instructions. Automatic allocation and management: Programs should be dynamically allocated across the memory hierarchy as required. Allocation should be transparent to the programmer. Thus, the programmer is relieved of concerns relating to memory limitations, and the operating system can achieve efficiency by assigning memory to jobs only as needed. Support of modular programming: Programmers should be able to define program modules, and to create, destroy, and alter the size of modules dynamically. Protection and access control: Sharing of memory, at any level of the memory hierarchy, creates the potential for one program to address the memory space of another. This is desirable when sharing is needed by particular applications. At other times, it threatens the integrity of programs and even of the

2.4 A system call is used by an application program to invoke a function provided by the operating system. Typically, the system call results in transfer to a system program that runs in kernel mode. 2.5 The system operator can review this quantity to determine the degree of "stress" on the system. By reducing the number of active jobs allowed on the system, this average can be kept high. A typical guideline is that this average should be kept above 2 minutes [IBM86]. This may seem like a lot, but it isn't.

CHAPTER 3 PROCESS DESCRIPTION AND

CONTROL

A A N S W E R S T ON S W E R S T O QQ U E S T I O N SU E S T I O N S

3.1 An instruction trace for a program is the sequence of instructions that execute for that process. 3.2 New batch job; interactive logon; created by OS to provide a service; spawned by existing process. See Table 3.1 for details. 3.3 Running: The process that is currently being executed. Ready: A process that is prepared to execute when given the opportunity. Blocked: A process that cannot execute until some event occurs, such as the completion of an I/O operation. New: A process that has just been created but has not yet been admitted to the pool of executable processes by the operating system. Exit: A process that has been released from the pool of executable processes by the operating system, either because it halted or because it aborted for some reason. 3.4 Process preemption occurs when an executing process is interrupted by the processor so that another process can be executed. 3.5 Swapping involves moving part or all of a process from main memory to disk. When none of the processes in main memory is in the Ready state, the operating system swaps one of the blocked processes out onto disk into a suspend queue, so that another process may be brought into main memory to execute. 3.6 There are two independent concepts: whether a process is waiting on an event (blocked or not), and whether a process has been swapped out of main memory (suspended or not). To accommodate this 2 × 2 combination, we need two Ready states and two Blocked states. 3.7 1. The process is not immediately available for execution. 2. The process may or may not be waiting on an event. If it is, this blocked condition is independent of the suspend condition, and occurrence of the blocking event does not enable the process to be executed. 3. The process was placed in a suspended state by an agent; either itself, a parent process, or the operating system, for the purpose of preventing its execution. 4. The process may not be removed from this state until the agent explicitly orders the removal. 3.8 The OS maintains tables for entities related to memory, I/O, files, and processes. See Table 3.10 for details.

constraints related to the amount of memory devoted to the process state for each process. At most N processes can be in the Running state, one for each processor. b. Zero is the minimum number of processes in each state. It is possible for all processes to be in either the Running state (up to N processes) or the Ready state, with no process blocked. It is possible for all processes to be blocked waiting for I/O operations, with zero processes in the Ready and Running states. 3.3 a. New → Ready or Ready/Suspend : covered in text Ready → Running or Ready/Suspend : covered in text Ready/Suspend → Ready : covered in text Blocked → Ready or Blocked/Suspend : covered in text Blocked/Suspend → Ready /Suspend or Blocked : covered in text Running → Ready, Ready/Suspend, or Blocked : covered in text Any State → Exit : covered in text b. New → Blocked, Blocked/Suspend, or Running : A newly created process remains in the new state until the processor is ready to take on an additional process, at which time it goes to one of the Ready states. Ready → Blocked or Blocked/Suspend: Typically, a process that is ready cannot subsequently be blocked until it has run. Some systems may allow the OS to block a process that is currently ready, perhaps to free up resources committed to the ready process. Ready/Suspend → Blocked or Blocked/Suspend: Same reasoning as preceding entry. Ready/Suspend → Running: The OS first brings the process into memory, which puts it into the Ready state. Blocked → Ready /Suspend : this transition would be done in 2 stages. A blocked process cannot at the same time be made ready and suspended, because these transitions are triggered by two different causes. Blocked → Running : When a process is unblocked, it is put into the Ready state. The dispatcher will only choose a process from the Ready state to run Blocked/Suspend → Ready : same reasoning as Blocked → Ready /Suspend Blocked/Suspend → Running : same reasoning as Blocked → Running Running → Blocked/Suspend : this transition would be done in 2 stages Exit → Any State : Can't turn back the clock 3.4 The following example is used in [PINK89] to clarify their definition of block and suspend: Suppose a process has been executing for a while and needs an additional magnetic tape drive so that it can write out a temporary file. Before it can initiate a write to tape, it must be given permission to use one of the drives. When it makes its request, a tape drive may not be available, and if that is the case, the process will be placed in the blocked state. At some point, we assume the system will allocate the tape drive to the process; at that time the process will be moved back to the active state. When the process is placed into the execute state again it will request a write operation to its newly acquired tape drive. At this point, the process will be move to the suspend state, where it waits for the completion of the current write on the tape drive that it now owns.

The distinction made between two different reasons for waiting for a device could be useful to the operating system in organizing its work. However, it is no substitute for a knowledge of which processes are swapped out and which processes are swapped in. This latter distinction is a necessity and must be reflected in some fashion in the process state. 3.5 Figure 9.3 in Chapter 9 shows the result for a single blocked queue. The figure readily generalizes to multiple blocked queues. 3.6 Penalize the Ready, suspend processes by some fixed amount, such as one or two priority levels, so that a Ready, suspend process is chosen next only if it has a higher priority than the highest-priority Ready process by several levels of priority. 3.7 a. A separate queue is associated with each wait state. The differentiation of waiting processes into queues reduces the work needed to locate a waiting process when an event occurs that affects it. For example, when a page fault completes, the scheduler know that the waiting process can be found on the Page Fault Wait queue. b. In each case, it would be less efficient to allow the process to be swapped out while in this state. For example, on a page fault wait, it makes no sense to swap out a process when we are waiting to bring in another page so that it can execute. c. The state transition diagram can be derived from the following state transition table: Next State Current State (^) ExecutingCurrently^ Computable (resident) (outswapp^ Computableed) states (resident)^ Variety of wait Variety of wait states (outswapped) Currently Executing Rescheduled Wait Computable (resident) Scheduled^ Outswap Computable (outswapped) Inswap Variety of wait states (resident) Event satisfied Outswap Variety of wait states (outswapped) Event satisfied 3.8 a. The advantage of four modes is that there is more flexibility to control access to memory, allowing finer tuning of memory protection. The disadvantage is complexity and processing overhead. For example, procedures running at each of the access modes require separate stacks with appropriate accessibility. b. In principle, the more modes, the more flexibility, but it seems difficult to justify going beyond four.

CHAPTER 4 THREADS, SMP AND

MICROKERNELS

A A N S W E R S T ON S W E R S T O QQ U E S T I O N SU E S T I O N S

4.1 This will differ from system to system, but in general, resources are owned by the process and each thread has its own execution state. A few general comments about each category in Table 3.5: Identification: the process must be identified but each thread within the process must have its own ID. Processor State Information: these are generally process-related. Process control information: scheduling and state information would mostly be at the thread level; data structuring could appear at both levels; interprocess communication and interthread communication may both be supported; privileges may be at both levels; memory management would generally be at the process level; and resource info would generally be at the process level.

4. 2 Less state information is involved. 4.3 Resource ownership and scheduling/execution. 4.4 Foreground/background work; asynchronous processing; speedup of execution by parallel processing of data; modular program structure. 4.5 Address space, file resources, execution privileges are examples. 4.6 1. Thread switching does not require kernel mode privileges because all of the thread management data structures are within the user address space of a single process. Therefore, the process does not switch to the kernel mode to do thread management. This saves the overhead of two mode switches (user to kernel; kernel back to user). 2. Scheduling can be application specific. One application may benefit most from a simple round-robin scheduling algorithm, while another might benefit from a priority-based scheduling algorithm. The scheduling algorithm can be tailored to the application without disturbing the underlying OS scheduler. 3. ULTs can run on any operating system. No changes are required to the underlying kernel to support ULTs. The threads library is a set of application-level utilities shared by all applications. 4.7 1. In a typical operating system, many system calls are blocking. Thus, when a ULT executes a system call, not only is that thread blocked, but also all of the threads within the process are blocked. 2. In a pure ULT strategy, a multithreaded application cannot take advantage of multiprocessing. A kernel assigns one process

to only one processor at a time. Therefore, only a single thread within a process can execute at a time. 4.8 Jacketing converts a blocking system call into a nonblocking system call by using an application-level I/O routine which checks the status of the I/O device. 4.9 SIMD: A single machine instruction controls the simultaneous execution of a number of processing elements on a lockstep basis. Each processing element has an associated data memory, so that each instruction is executed on a different set of data by the different processors.. MIMD: A set of processors simultaneously execute different instruction sequences on different data sets. Master/slave: The operating system kernel always runs on a particular processor. The other processors may only execute user programs and perhaps operating system utilities. SMP: the kernel can execute on any processor, and typically each processor does self-scheduling from the pool of available processes or threads. Cluster: Each processor has a dedicated memory, and is a self-contained computer. 4.10 Simultaneous concurrent processes or threads; scheduling; synchronization; memory management; reliability and fault tolerance. 4.11 Device drivers, file systems, virtual memory manager, windowing system, and security services. 4.12 Uniform interfaces: Processes need not distinguish between kernel-level and user- level services because all such services are provided by means of message passing. Extensibility: facilitates the addition of new services as well as the provision of multiple services in the same functional area. Flexibility: not only can new features be added to the operating system, but existing features can be subtracted to produce a smaller, more efficient implementation. Portability: all or at least much of the processor-specific code is in the microkernel; thus, changes needed to port the system to a new processor are fewer and tend to be arranged in logical groupings. Reliability: A small microkernel can be rigorously tested. Its use of a small number of application programming interfaces (APIs) improves the chance of producing quality code for the operating-system services outside the kernel. Distributed system support: the message orientation of microkernal communication lends itself to extension to distributed systems. Support for object-oriented operating system (OOOS): An object-oriented approach can lend discipline to the design of the microkernel and to the development of modular extensions to the operating system. 4.13 It takes longer to build and send a message via the microkernel, and accept and decode the reply, than to make a single service call. 4.14 These functions fall into the general categories of low-level memory management, inter-process communication (IPC), and I/O and interrupt management. 4.15 Messages.

A A N S W E R S T ON S W E R S T O PP R O B L E M SR O B L E M S