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This course focuses on quantitative principle of computer design, instruction set architectures, datapath and control, memory hierarchy design, main memory, cache, hard drives, multiprocessor architectures, storage and I/O systems, computer clusters. This lecture includes: Set, Associative, Address, Block, Number, Mapping, Cache, Memory, Bytes, Bits, Main, Sets, Lines
Typology: Slides
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Address length = (s + w) bits Number of addressable units = 2s+w^ words or bytes Block size = line size = 2w^ words or bytes Number of blocks in main memory = 2d Number of lines in set = k Number of sets = v = 2d Number of lines in cache = kv = k * 2d Size of tag = (s – d) bits
Tag 9 bit (^) Set 13 bit Word2 bit
Let us see how it works? ─ the cache index selects a set from the cache. The two tags in the set are compared in parallel with the upper bits of the memory address.
─ If neither tag matches the incoming address tag, we have a cache miss
─ Otherwise, we have a cache hit and we will select the data on the side where the tag matches occur.
This is simple enough. What is its disadvantages?
Disadvantage of Set Associative Cache
First of all, a N-way set associative cache will need N comparators instead of just one comparator (use the right side of the diagram for direct mapped cache).
A N-way set associative cache will also be slower than a direct mapped cache because of this extra multiplexer delay.
Finally, for a N-way set associative cache, the data will be available AFTER the hit/miss signal becomes valid because the hit/miss is needed to control the data MUX.
Disadvantage of Set Associative Cache
