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The basics of sequential logic circuits and flip-flops. It covers the definition of sequential circuits, working of sequential circuits, clocks, triggering methods in flip-flops, difference between latch and flip-flop, truth table, characteristic table, and excitation table for SR flip-flop. useful for students studying digital electronics and computer science.
Typology: Summaries
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● A sequential circuit is a combination of a combinational circuit and a memory, where the output depends on the present input and the past outputs. ● A combinational circuit is one where the output depends only on the present inputs. ● An example of this is an adder, where the output depends only on the two inputs.
● Sequential circuits are used to store the past outputs and use them to calculate the present output. ● This is seen in counters, which add one to the previous output and then generate the next output. ● For example, if the counter is at 5, the next output will be 6. ● To do this, the circuit requires memory to store the previous output.
● A key feature of this circuit is the feedback, which is used in combination with the present input and the past output.
● People initially thought of using cascaded NOT gate arrangements to store a single bit. ● This memory element is also known as a flip-flop and can be demonstrated by two NOT gates. ● An input of 1 or high will result in an output of 0 from the first NOT gate and 1 from the second, thereby storing the bit.
● When S is 0 and R is 1, the output will be 1 0, resulting in Q being 0 and its complement being 1.
● When S and R are both 1, the resulting output is 0 0 which results in both Q and Q complement being 0, which is a contradiction.
● When S and R are 0, Q is equal to 1 and Q complement is equal to
● When S is 0 and R is 1, Q is equal to 0 and Q complement is equal to 1. ● Case 3 when S is 1 and R is 1 is not used in the SR latch as it leads to an unpredictable output.
● When S and R are 0, Q is equal to 0 and Q complement is equal to
● When S is 0 and R is 1, Q is equal to 1 and Q complement is equal to 0. ● Case 3 when S is 1 and R is 1 is the memory state and is used to store data.
3)What is a Clock?:
● A clock is a signal that goes from low to high, then down again, and repeats in a cycle with a 50% duty cycle. ● The cycle time is referred to as the time period and the frequency is 1/time period. ● By changing the clock frequency, it is possible to decide the speed of the circuit.
● Clocks are used to time processes in a sequential circuit, as the output of one process is the input of another and the processes should not operate randomly. ● In a sequential circuit, a clock signal (CLK) is given as an input to the flip-flop and the flip-flop will only be functional when the clock is high. ● The flip-flop can be designed to work when the clock is high or when the clock goes from low to high (known as leading edge triggering) or from high to low (known as falling edge triggering).
● The duty Cycle is the ratio of the time for which a signal is high to the total time. ● In the case of a clock signal, the duty cycle is 50%, as it is high for 50% of the time. ● The duty cycle is important as it prevents the output of a circuit from changing randomly due to stray signals.
5)Difference between Latch and Flip Flop:
● This covers the difference between latches and flip-flops, a common question in digital electronics. ● A circuit is shown, an SR latch without a control input, and it is not suitable for use. ● Two more NAND gates are needed to introduce a control input, and this circuit can be used as a latch or a flip-flop.
● The circuit operates as a latch when the control input is not a clock, or in other words, when it is level triggered. ● Whenever the control input is high, the latch will operate. ● If the control input is something like a random enable signal, then the circuit will be operational when the enable is high for a period, and will not be operational when the enable is low for a period.
● The circuit will act as a flip-flop when there is a clock input in place of the enabled input. ● The clock has a duty cycle of 50%, and the circuit is only operational when the clock is transitioning from low to high, or vice versa. ● The circuit will check for the input and be operational only when the clock is changing, and this is called edge triggering.
● A latch is level sensitive and will check the input whenever there is one, while a flip-flop checks the input and is only operational when the clock is changing.
6)Introduction to SR Flip Flop:
● SR Flip Flop is a circuit consisting of a latch with NAND gates. ● The truth table for the SR Flip Flop is very important and can be used to develop the characteristic table in the next presentation.
● When S* and R are 0, the values of Q and Q complement are indeterminate. ● When S* is 1 and R is 0, the value of Q is 1 and the value of Q complement is 0. ● When S* is 0 and R is 1, the value of Q is 0 and the value of Q complement is 1. ● When S* and R are both 1, the previous value of Q is stored.
● A clock is used as a control input to prevent accidental changes in the input. ● The value of S* is equal to S and the clock, and the value of R* is equal to the R complement and clock.
● The symbol for an SR Flip-Flop is a box, with three inputs (S, R, and clock) and two outputs (Q and Q complement). ● The arrow indicates that it is an edge-triggered Flip-Flop.
● The main purpose for introducing a clock in latches is to make them controlled. ● When the clock is set to one, the values of S and R are S-Complement and R-Complement respectively.
7)Truth Table, Characteristic Table, and Excitation Table for SR Flip Flop:
● The last presentation saw the basic of the SR flip-flop and ended with the creation of the truth table. ● In this presentation, the characteristic table and the excitation table for the SR flip-flop will be found.
● The truth table is familiar, with the clock input being low and the value output being QN+1. ● QN+1 is the next state, and QN is the present state. ● When the clock is high, the inputs S and R determine the next state, which is QN+1. ● When the clock is low, it is always in memory and the next state is equal to the present state, QN.
● The characteristic table has three inputs (QN, S, R) and the output is QN+1. ● There are eight possible combinations. ● When S and R are both 0 and the clock is high, QN+1 is equal to Q and N is 0. ● When S is 0 and R is 1, QN+1 is 1. ● When S is 1 and R is 0, QN+1 is 0. ● When S and R are both 1, this is an invalid configuration for the SR flip-flop.
● The excitation table has two inputs (QN and QN+1) and two outputs (S and R). ● When QN and QN+1 are both 0, S is 0 and R is 1. ● When QN is 0 and QN+1 is 1, S is 1 and R is 0. ● When QN and QN+1 are both 1, S is 0 and R is 0.
● The value of S is always 0. ● This can be written as equal to 0.
● The value of R is 0 1. ● This is a "don't care" value.
● When QN is 0 and QN Plus 1 is 1, S is 1 and R is 0.
● When QN is 1 and QN Plus 1 is 0, S is 0 and R is 1.
● The last case when QN and QN Plus 1 is that the green ones are always 0. ● S is changing from 0 to 1 and is a "don't care" value.
● To find the value of QN Plus 1, make an 8-cell K map with the inputs QN, S, and R. ● The first group is 1, and the second group is -. ● From the first group, the value is S. ● From the second group, the value is QN.
8)Introduction to D flip flop:
● D flip-flops are used to store data by giving a single input and complementing the other. ● D flip-flops are derived from SR flip-flops, where S and R must always complement each other. ● In a D flip-flop, if the input is 0 then the output is 1, and if the information is 1 then the output is 0.
● To make a D flip-flop, an inverter is used to extend the input and the output of the inverter is given to R. ● The same input is then called D and the clock is used to store the data. ● The truth table for a D flip-flop is very simple, where the clock is 0 and the output is the same as the previous inputs.
9)Introduction to JK flip flop:
● Already studied the SR and D flip-flops, so what is the need to study the JK flip-flop? ● SR and D flip-flops have the disadvantage of the last combination when S is 1 and R is in a non-used state. ● The JK flip-flop fixes this disadvantage by utilizing this last combination in a useful way.
● Take the Q output and give it to a NAND gate in which R is one of the inputs. ● Take the Q complement output and give it to the same NAND gate in which S is one of the inputs. ● This makes the circuit for the JK flip-flop.
● When the clock is low, the inputs to the NAND SR latch are 1, so the output is stored in memory. ● When the clock is high and J and K are 0, there will be no change to the outputs. ● When the clock is high and J is 0 and K is 1, the output will be Q = 0 and Q complement = 1. ● When the clock is high and J and K are both 1, the output will be Q = 1 and Q complement = 0.
● Input will change the value of Q from 0 to 1. ● Q complement will become 0, and 1 plus its complement will give
● Q is racing from 0 to 1, and its complement is also racing from 0 to
10)Truth Table, Characteristic Table, and Excitation Table for JK flip flop:
● In the last presentation, the working of the JK flip-flop was seen and a truth table was deduced. ● The truth table is the same as that of the SR flip-flop, but the last combination is a toggle where the output Qn+1 quickly changes from 0 to 1 and then again to 0.
● The characteristic table is dependent on the present inputs (J and K) and the previous state (Qn). ● When J and K are both 0, the output (Qn+1) is the same as the previous state (Qn). ● When J is 0 and K is 1, the output (Qn+1) is 0. ● When J is 1 and K is 0, the output (Qn+1) is 1. ● When J and K are both 1, the output (Qn+1) is the complement of the previous state (Qn).
● The excitation table is deduced from the characteristic table and contains two inputs (Qn and Qn+1) and two outputs (J and K). ● When Qn and Qn+1 are both 0, J is 0 and K is 0 or 1. ● When Qn is 0 and Qn+1 is 1, J is 1 and K is 0 or 1. ● When Qn is 1 and Qn+1 is 0, J is 0 or 1 and K is 1. ● When Qn and Qn+1 are both 1, J is a don't care and K is 1.
● The value of K is 1 and only two cases remain.
● J changes from 0 to 1 and K is 0. ● This is the last case in the excitation table.
● Variables are Q1 and Q1+1. ● Fill the map with 0, 1, and Don't Care. ● The combination is easy due to single 1, thus J is equal to Q1+1.
● Variables are QN and QN+1. ● Fill the map with 0, 1, and Don't Care. ● Group 1 has a QN complement and J is 1. ● Group 2 has QN, thus J is 0 and K is QN+1 complement.
● A 3-variable K map is required. ● Fill the map with 0, 1, and Don't Care. ● Group 1 has a QN complement and J is 1. ● Group 2 has QN, thus J is 0 and K is QN+1 complement. ● This is the value of QN+1 from the excitation table.
● Edge triggering can also be used to overcome racing, as it does not give the circuit enough time to raise. ● The most popular way to overcome racing is by using a master/slave configuration.
● Master/Slave configuration is widely used and has many advantages. ● It allows for fast and reliable operation of the flip-flop circuit. ● It ensures that the output is generated quickly and accurately.
● The presenter asks for feedback from viewers on the lectures. ● This includes the speed, pronunciation, and pitch of the presenter's lectures. ● The presenter encourages viewers to give suggestions to improve future lectures.
12)Master Slave JK Flip Flop:
● The last presentation discussed how the output of a JK flip-flop changes in a manner known as de-racing, which is an undesired output. ● The methods for overcoming the racing are keeping the clock half-time period that is T by 2 less than the propagation delay of the flip-flop, edge triggering, and master-slave operation.
● To eliminate the effect of the feedback, another stage is added and the feedback is removed. ● The output is connected to the input of the second stage and the feedback is connected to the output of the first stage. ● Two important points in master-slave operation are connecting the feedback and the clock. ● The clock is complemented and given to the slave. ● The master is operational when the clock is high, and the slave is operational when the clock is low. ● When the output changes there is no effect on the feedback because the clock is low.
● The output of the master changes when the clock is high, and the output of the slave changes when the clock is low. ● The output QM changes and the output Q remains the same when the clock is high. ● When the output changes, the clock is low so the master is not operational, eliminating the effect of the feedback and hence the racing.
