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University of California at Berkeley College of Engineering Department of Electrical Engineering and Computer Sciences Computer Science Division
CS 152 J. Wawrzynek Spring 1994 Handout #
Computer Architecture and Engineering
Midterm I I
Your Name:
ID Numb er:
This is a closed-book, closed-note exam. You have 90 minutes. You might not have
time to complete all the questions, so read them all rst. Each question is marked with
its numb er of p oints (one p oint p er exp ected minute of time).
Show your work. Write neatly and b e well organized.
Go o d luck!
problem maximum score
1 10pts
2 15pts
3 30pts
4 15pts
5 20pts
total 90pts
- [10 p oints]
Consider the design of three separate caches, a directed mapp ed version (DM), a two-way set asso ciative version (SA), and a fully asso ciative version (FA). The total cache size in data words for each is 1K words and cache blo cks (lines) contain four words of data. Assuming a 16-bit memory address, ll in the table b elow to indicate how many bits of the address to assign to each eld.
DM SA FA
byte in word (byte)
(tag)
set identi er (set)
word in blo ck (word)
For each cache version, illustrate the breakdown of the address into elds. Lab el each eld using the names in parenthesis in from the table ab ove.
DM:
SA:
FA:
- [30 p oints] Short answers. Please provide short answers to the following questions. If you do not know the answer, leave it blank. Correct answers are worth the numb er of p oints indicated by each question, blanks are worth zero, and incorrect answers minus the numb er of p oints indicated.
(a) [1 p oints] What is the maximum theoretical sp eed-up for a n-stage pip eline pro cessor over a \single-cycle" pro cessor implementation?
(b) [2 p oints] List two reasons why in (a) the sp eedup will actually b e less in practice.
(c) [1 p oints] For a standard MIPS implementation, approximately what p ercentage of branch delay slots would you exp ect could b e lled?
(d) [2 p oints] Data forwarding can solve some data hazards in pro cessor pip elines. Brie y, how do es forwarding e ect the pro cessor cost?
(e) [1 p oints] True or False. A two-bit branch prediction scheme will always miss-predict less than a one-bit scheme.
(f ) [1 p oints] Rank order the three cache organizations according to miss rate.
(g) [1 p oints] Rank order the three cache organizations according to implementation cost.
(h) [2 p oints] In what way do es a system with a write-back cache achieve a p erformance advantage over a write-through cache?
(i) [1 p oints] In what way is a write-back cache more complex than a write-through cache?
(j) [1 p oints] True or False. Because of its simplicity, one-transistor Dynamic RAM cells are usually used for register le implementations.
(k) [3 p oints] What is the approximate data bandwidth out of a frame bu er to feed a 1K X 1K pixel color display device?
(l) [2 p oints] What are three factors that contribute to the time needed to access a blo ck from a magnetic disk?
(m) [1 p oints] True or False. Unlike ethernet, token-ring networks use no arbitration scheme.
(n) [2 p oints] What is the primary advantage of asynchronous bus signalling over syn- chronous?
(o) [1 p oints] True or False. The primary disadvantage of a vector pro cessor over a sup er-pip elin ed pro cessor is that the vector pro cessor requires multiple execution units.
(p) [2 p oints] List two limiters of sup er-scalar pro cessor p erformance.
(q) [2 p oints] List two limiters of sup er-pip eline d pro cessor p erformance.
(r) [1 p oints] Name one commercial SIMD parallel computer system.
(s) [2 p oints] True or False. The theoretically lowest diameter network for multipro cessor is a hyp ercub e top ology.
(t) [1 p oints] True or False. All massively parallel pro cessors use a message passing mo del for inter-pro cessor communication.
(d) Would you exp ect that the average CPI would go up or down with this change to the pip eline? Justify your answer.
