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Review Questions for MIPS Processors, Exams of Computer Architecture and Organization

Review Questions for MIPS Processors

Typology: Exams

2019/2020

Uploaded on 02/07/2020

huseyinguney
huseyinguney 🇹🇷

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Questions:
1. Find the equivalent decimal number for the following FP numbers which are represented
in machine code using MIPS FP number formats.
a. 0100 0010 0111 1101 0000 0000 0000 0000
b. 0100 0000 0100 1111 1010 0000 0000 0000 0000 0000 0000 0000 0000 0000
0000 0000
c. 1011 1111 0100 1000 0000 0000 0000 0000
d. 1100 0000 0110 0001 1011 1010 0000 0000 0000 0000 0000 0000 0000 0000
0000 0000
Note: You are not allowed to use a calculator. So that you may leave the results in the
fraction form (base 10) only if it is not possible to calculate by hand.
2. According to MIPS load instruction execution time table below, answer the following
questions.
a. What will be the duration of Non-pipelined execution clock-cycle for load
word instruction? (Hint: Duration of each clock-cycle)
b. What will be the duration of Pipelined execution clock-cycle for load word
instruction? (Hint: Duration of each clock-cycle)
c. If the MIPS processor is non-pipelined; what will be the total execution time
for the following instructions?
i. lw $s1, 100($s0)
ii. lw $s2, 200($s0)
iii. lw $s3, 300($s0)
d. If the MIPS processor is pipelined; what will be the total execution time for the
instructions in section c above?
e. Draw the pipelining diagram for the load instructions in section c above. Show
clock-cycles and stages of pipelining clearly using MIPS pipelining
architecture.
3. Find the hazards in the following code segment and reorder the instructions to avoid any
pipeline stalls. Assume that forwarding is enabled for the pipelining.
Consider the following code segment in C:
a = b + e;
c = b + f;
pf3
pf4

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Questions:

  1. Find the equivalent decimal number for the following FP numbers which are represented in machine code using MIPS FP number formats. a. 0100 0010 0111 1101 0000 0000 0000 0000 b. 0100 0000 0100 1111 1010 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 c. 1011 1111 0100 1000 0000 0000 0000 0000 d. 1100 0000 01 10 0001 1011 1 01 0 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 Note : You are not allowed to use a calculator. So that you may leave the results in the fraction form (base 10) only if it is not possible to calculate by hand.
  2. According to MIPS load instruction execution time table below, answer the following questions. a. What will be the duration of Non-pipelined execution clock-cycle for load word instruction? ( Hint: Duration of each clock-cycle) b. What will be the duration of Pipelined execution clock-cycle for load word instruction? ( Hint: Duration of each clock-cycle) c. If the MIPS processor is non-pipelined; what will be the total execution time for the following instructions? i. lw $s1, 100($s0) ii. lw $s2, 200($s0) iii. lw $s3, 300($s0) d. If the MIPS processor is pipelined; what will be the total execution time for the instructions in section c above? e. Draw the pipelining diagram for the load instructions in section c above. Show clock-cycles and stages of pipelining clearly using MIPS pipelining architecture.
  3. Find the hazards in the following code segment and reorder the instructions to avoid any pipeline stalls. Assume that forwarding is enabled for the pipelining. Consider the following code segment in C: a = b + e; c = b + f;

And, the equivalent MIPS code for this segment, assuming all variables are in memory and are addressable as offsets from $t0:

  1. Draw the pipeline stage diagram and show stalls for the following MIPS instruction set.
  2. Write down names and draw four computer architecture classes according to the number of instruction streams and data streams.
  3. Convert the following C code segment to the MIPS assembly code? // Procedure CountNum to add numbers from 0 to 9. int CountNum() { int sum = 0; int i; for(i = 0; i != 10; i = i + 1) sum = sum + i; return sum; } Hints: a. Define the required registers for this procedure. b. Store all registers in the stack that you are going to use in your code except temporary registers. c. Adjust / Restore Stack for all registers. d. Use proper registers and instructions for the procedure body. Appendix: MIPS Reference Data Sheet lw $t1, 0($t0) lw $t2, 4($t0) add $t3, $t1, $t sw $t3, 12($t0) lw $t4, 8($t0) add $t5, $t1, $t sw $t5, 16($t0) sw $s1, 12($s0) lw $s1, 8($s0) beq $s2, $s3, Label # Assume $s2 != $s add $s2, $s4, $s slt $s2, $s5, $s