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Chapter 5: Processors

• Chapter 5: Processors – 1

CS140 Computer Organization

Chapter 5 Objectives

• Understand the factors involved in instruction set architecture

design.

• Gain familiarity with memory addressing modes.
• Understand the concepts of instruction-level pipelining and its

affect upon execution performance.

• Chapter 5: Processors – 2

This chapter is divided into two parts:

• An overview of instruction formats.
• Digging into the guts of processor design.

• If we have a two-byte integer, the integer may be stored so that the

least significant byte is followed by the most significant byte or vice

versa.

• In little endian machines, the least significant byte is followed by the most significant byte.
• Big endian machines store the most significant byte first (at the lower address). - Chapter 5: Processors – 4

Byte ordering, or endedness , is a major architectural consideration.

As an example, given the hexadecimal number 12345678.

The big endian and small endian arrangements of bytes are shown:

Formats:

• Endedness
• Register Mechanism
• Instruction layout
• Data types supported
• Addressing modes

gcc -g quickie.c – o quickie quickie od -b Tempfile 003 000 000 000 021 000 000 000 001 002 000 000 – Chapter 5: Processors – 5

#include <stdio.h> #include <stdlib.h> #include <string.h>

*typedef struct { int val1; int val2; int val3; } RECORD; main() { RECORD r; FILE FOutput;

*r.val1 = 3; r.val2 = 17; r.val3 = 513; FOutput = fopen( "Tempfile", "w" ); fwrite( (char )(&r), sizeof(RECORD), 1, FOutput ); fclose( FOutput ); }

This shows a small program that writes data to a file. What’s unusual here is that the data written is three integers. Note how this data is laid out in the file.

Formats:

• Endedness
• Register Mechanism
• Instruction layout
• Data types supported
• Addressing modes

• Chapter 5: Processors – 7

Formats:

• Endedness
• Register Mechanism
• Instruction layout
• Data types supported
• Addressing modes

General purpose register (GPR) architecture, registers used instead of memory.

• Faster than accumulator architecture.
• Efficient implementation for compilers.
• Results in longer instructions.
• Most systems today are GPR systems.
• There are three types:
• Memory-memory where two or three operands may be in memory.
• Register-memory where at least one operand must be in a register.
• Load-store where no operands may be in memory.
• The number of operands and the number of available registers has a direct affect on instruction length.

Stack Machines

• Stack machines use one - and zero-operand instructions.
• LOAD and STORE instructions require a single memory address operand.
• PUSH and POP operations involve only the stack’s top element.
• Binary instructions (e.g., ADD , MULT ) use the top two items on the stack.
• Think differently!
• We are accustomed to writing expressions using infix notation, such as: Z = X
  • Y.
• Stack arithmetic requires that we use postfix notation: Z = XY+.
  • This is also called reverse Polish notation , (somewhat) in honor of its Polish inventor, Jan Lukasiewicz (1878 - 1956). - Chapter 5: Processors – 8

Formats:

• Endedness
• Register Mechanism
• Instruction layout
• Data types supported
• Addressing modes

In a one-address ISA, like PIC, the expression, Z = X  Y + W  U looks like this: movfw X mult Y ; We haven’t seen mult movwf TEMP movfw W mult U add TEMP movwf Z

• Chapter 5: Processors – 10

Accumulator Machines

Formats:

• Endedness
• Register Mechanism
• Instruction layout
• Data types supported
• Addressing modes

In a CISC GPR, (e.g.,Intel), the expression, Z = X  Y + W  U might look like this: LOAD R1,X MULT R1,Y LOAD R2,W MULT R2,U ADD R1,R STORE Z,R

CISC GPR

With a three-address ISA, (MIPS), the expression,

Z = X  Y + W  U might look like this: LW R1, X LW R2, Y MULT R3, R1, R LW R4, W LW R5, U MULT R6, R4, R ADD R3, R3, R SW R3, Z

• Chapter 5: Processors – 11

3-Address RISC GPR

Formats:

• Endedness
• Register Mechanism
• Instruction layout
• Data types supported
• Addressing modes

Instruction Layout

• A system has 16 registers and 4K of memory.
• We need 4 bits to access one of the registers. We also need 12 bits for a memory address.
• If the system is to have 16-bit instructions, (and we want 4 bits for the opcode), we have two choices for our instructions: - Chapter 5: Processors – 13

Formats:

• Endedness
• Register Mechanism
• Instruction layout
• Data types supported
• Addressing modes
• If we allow the length of the opcode to vary, we could create a very rich instruction set:

Is there something missing

from this instruction set? Docsity.com

Data Types Supported

Instructions fall into several broad categories that you

should be familiar with:

• Data movement.
• Arithmetic.
• Boolean.
• Bit manipulation.
• I/O.
• Control transfer.
• Special purpose.
  • Chapter 5: Processors – 14

Can you think of some examples of each of these?

Formats:

• Endedness
• Register Mechanism
• Instruction layout
• Data types supported
• Addressing modes

Addressing Modes

Immediate addressing is where the data is part of the instruction. In PIC Assembly movlw 0x27 moves the hex value 0x27 into the accumulator – the 0x27 was stored in the instruction.

• Chapter 5: Processors – 16

Formats:

• Endedness
• Register Mechanism
• Instruction layout
• Data types supported
• Addressing modes

Register addressing is where the data is located in a register. In MIPS Assembly, add R6, R1, R2 , we’re adding the data that’s in register R1 to the data that’s in register R2 and putting the sum into register R6.

Direct addressing is where the address of the data is given in the instruction. In PIC Assembly, movfw Addr says to move the data stored at location Addr into the accumulator. An equivalent MIPS instruction is lw R5, Addr - move the contents of Addr into R

Addressing Modes

• Chapter 5: Processors – 17

Formats:

• Endedness
• Register Mechanism
• Instruction layout
• Data types supported
• Addressing modes

Indirect addressing gives the address of the

address of the data in the instruction. The PIC Assembler uses this mode: movlw 0x20 ; Get an address movwf FSR ; Store that address movfw INDF ; Read data at location with that address

Register indirect addressing uses a register to store the address of the address of the data. MIPS Assembly uses lw R6,(R1). This means, take the contents of R1 as an address. Look in that address to find the data.

Addressing Modes

For the instruction shown, what value is

loaded into the accumulator for each addressing mode?

• Chapter 5: Processors – 19

Formats:

• Endedness
• Register Mechanism
• Instruction layout
• Data types supported
• Addressing modes

MIPS Code lw R6, 800 lw R7, Location lw R8, (R6) lw R9, 800(R6)

Location:

R6 = R7 = R8 = R9 =

Addressing Modes

For the instruction shown, what value is

loaded into the accumulator for each addressing mode?

• Chapter 5: Processors – 20

Formats:

• Endedness
• Register Mechanism
• Instruction layout
• Data types supported
• Addressing modes

MIPS Code lw R6, 800 lw R7, Location lw R8, (R6) lw R9, 800(R6)

Location:

R6 = 800 R7 = 900 R8 = 1000 R9 = 700