Computer Architecture Midterm: New Instructions Implementation & Critical Path Calculation, Exams of Computer Architecture and Organization

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CS152: Computer Architecture and Engineering

Fall, 2000

Midterm 1

Professor W. Brodersen

Problem 1: Single-cycle Processor Performance (35 points)

We have a single cycle processor as we learned in class. Besides the instructions R-format, lw, sw, and beq that the processor already implemented, the designer figured that certain software does the following instructions extensively cs $t $sl $s2 cslw $t $sl $s2 cslwcs $t $sl $s

Besides the usual PC handling and instruction fetch as before,

• the cs instruction is described as: $t <= max($sl, $s2)
• The cslw does the following: $t <=memory [max($sl,$s2)]
• The cslwcs instruction the following: $t <= max{$sl, memory[max ($s1, $s2)]}

So now you see that cs and 1w in above names stand for “compare select” and "load word".

The designer plans to modify the datapath and control signal based on the processor showed in next page. It's a textbook processor with some missing blocks and wiring to fill in. The components that can be used are any of the blocks already present in the design and the generalized GALU (showed above) with an additional output GREATER that equals to 1 if Input1-Input2 >0, and equals to 0 if Input1-Input2 =< 0.

ii) For cslwcs:

Box 2

Mux c output To Reg file write data

B) [7 points] Fill in the control table below with X, 0 or 1. Add in new columns) if you need new control signal(s). You may not need all three columns.

Instruction ALUsrc Mem- ToReg RegWr^

Mem- Read

Mem- Write SW 1 0 0 1 R-format 0 0 0 cslw cslwcs

C) [9 points] You will point out the critical path, calculate the critical path delay in ns, and hence determine the fastest clock rate in MHz. Finally, you will use some program features to calculate the execution tine of the processor. Use the following delay parameters (ignore hold time and regard the register delay as clock-to-Q):

• ALU or GALU, delay = 15 (ns)
• Sign/zero extender, delay = 3(ns)
• 2-1 Mux, delay = 2 (ns)
• Memory, delay (both write and read) = 10 (ns)
• Register, delay = 1 (ns)
• Register files, read delay =10 (ns), write setup time=10 (ns) All other components' delays are ignored (i.e. zero).

i) The critical, path is (write down the components' names in order):

ii) The critical path delay in ns and the fastest clock rate in MHz:

iii) Now use a program to evaluate the performance of the processor. The program has 10% lw instructions, 10% beq , 10% sw , 20% R-format, 25% cs , 15% cslw , 10% cslwcs. The program contains 1,000,000 instructions in total. How much time is needed to run this program?

Problem 2: Bus-based Multicycle Processor (30 points)

The datapath below forms a multicycle processor which uses two time-multiplexed buses for communication rather than point-to-point connections and muxes. What are the pros and cons of such an architecture? Is it a good idea? This problem will get you started toward a decision...

You can make the following assumptions:

• The next PC logic will automatically increment the PC when you fetch a new instruction
• Both the sign-extended and zero-extended forms of the immediate field are available to Bus B
• The register specifiers Rs, Rt, and Rd are always correctly passed to the register file (data written into the register file is passed from BusB)
• Both the register file and the memory have purely combinational (asynchronous) reads
• The register file, memory, and all registers are triggered by the same clock edge (with no skew)

You can use the rest of this page for scratch space. The first question begins on the next page...

A) [10 points] Microprogram the following instructions by filling in the table. The SrcA and SrcB fields specify which signals will be assigned to BusA and BusB, respectively. The WrDest field specifies what component is written at the end of the cycle. This can be any one of the state registers (A and B can be paired together in one cycle), the register file, or memory. It is implied that all other components will not be written accidentally. The Sequence field behaves as presented in class: it specifies whether the microprogram should return to the fetch stage to start a new macroinstruction, dispatch to a location specific to the current opcode, or proceed in order. You should ignore the BNE instruction for now - it is only provided for part (C). Hint: you do not need to fill all the rows. μAddr Instruction SrcA SrcB ALUOp WrDest Sequence

00 Fetch 01 Decode 02 ADD 03 04 05 06 ADDI 07 08 09 0A LW 0B 0C 0D 0E SW 0F 10 11

(^12) BNE A B Sub --

If ALUZero Then Next Else Fetch 13 PC SX Add PC* Fetch

Problem 3: MIPS 5 Stage Pipelined Processor (35 points) The processor shown on the next page is one implementation of a standard MIPS 5 stage pipelined processor. The specifications of the processor are as follows:

• Five pipeline stages: IF, ID, EX, MEM, WB.
• The processor does not have forwarding nor hazard implemented yet.
• Control signal are represented by dotted lines. Control bus values represent the actual control bits top-down. Control signal values are in binary format. Data signal values are in decimal format.
• RegisterFile writes in the first half of the cycle , and reads in the second half.
• Both instruction and data memory reads asynchronously; data memory writes synchronously. Both memories are byte addressed. Data memory size is 16 words and only the least significant bits are used to address the memory. Each component has been labeled with a worst-case delay. Registers only have clock-to-Q delay, and zero setup/hold time. Assume no clock skew.
• The diagram of the processor also includes a snapshot of the processor at the beginning of the cycle , with necessary signal values labeled.
• Tables 1 & 2 show the contents of the register file and data memory at the snapshot time. Assume the register file and memory have been correctly updated in the previous cycle, but all writes in the current cycle have not taken place yet. Table 3 shows the ALU control truth table. A MIPS R3000 opcode table is also attached at the end.

A) [5 points] How many branch delay slot(s) does this processor have?

B) [5 points] What is the minimum clock period of the processor?

C) [7 points] In MIPS assembly language, determine exactly what instruction is being executed in ID stage? What are the changes to the register file and data memory after the completion of the instruction?

D) [7 points] In MIPS assembly language, determine exactly what instruction is being executed in EX stage? What are the changes to the register file and data memory after the completion of the instruction?

E) [11 points] Now implement only the hazard detection unit without forwarding, such that from the software's perspective, the processor has exactly one branch delay slot, exactly one load delay slot, and all hazards are resolved at the hardware level. You are only allowed to add write enable control signals to any of the five pipeline registers, along with necessary control logic. i. In order to stall the pipeline, some of the five pipeline registers should have write enable control signal. Fill in the following table. ('Y' means yes needed, `N' means not necessary) PC IF/ID ID/EX EX/MEM MEM/WB Need Write En?

ii. Describe in words, or pseudocode, under what condition each of the pipeline registers should be write disabled, and for how many processor cycles in each case. Pipeline Register

Write Disable Condition Number of Cycles PC

IF/ID

ID/EX

EX/MEM

MEM/WB