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DIFFERENT POWER OPTIMIZATION
TECHNIQUES FOR LOW POWER VLSI
CIRCUITS
Abstract
CMOS technology is the key element within the development of VLSI systems since it consumes less power. Power improvement has become associate with overridden concern within the submicron CMOS technologies. thanks to shrinking in the size of the device, reduction in power consumption and overall power management on the chip are the key challenges. for several styles, power improvement is very important to cut back package value and to increase battery life. In power improvement leak additionally plays a vital role as a result of it's a big fraction within the total power dissipation of VLSI circuits. This paper aims to elaborate on the developments and advancements within the space of power utilization of CMOS circuits in the deep submicron region. This survey is helpful for the designer in choosing an appropriate technique relying upon the necessity.
Keywords
low power, leakage power, system-level, architecture level, voltage scaling, transistor stacking, power gating, adiabatic logic.
1. INTRODUCTION
Energy utilization is that the important feature of recent electronic systems, because of the desirability of transportable devices, demand for reliableness and performance, to increase battery life, got to scale back package value, to cut back inexperienced value, etc. [1]. Advancements in scaling with reduced threshold and provide voltages result in raised leakages in MOS transistors. several studies are given that leakage power consumption is up to four-hundredth of total power consumption in nm technology [2]. to beat the power dissipation drawback several researchers have planned completely different concepts from the device level to the study level. However, there are no universal thanks to avoiding trade-offs between power, delay, and area. Thus, designers are needed to decide on applicable techniques that satisfy application and merchandise wants. In VLSI circuits, to manage the power consumption provide voltage plays a crucial role. provide voltage scaling while not scaling of threshold voltage degrades the performance of the device [3]. The reduction of threshold voltage and provide voltages proportionately retains the performance. the threshold voltage reduction results in 5 times higher leakage current [4]. the necessities for power optimization still increase considerably and also the motivations to optimize power dissent from application to application. Power consumption has become a primary style issue and desires appropriate power management within the design of digital circuits wherever switch and standby mode affects the performance of the system. the planning of a low power circuit primarily focuses on an issue that occurred because of the performance, power dissipation, and chip size.
This paper is organized as follows in section-1 we tend to mention the sources of power dissipation in CMOS. In section II we tend to mention the power optimization at totally different levels of abstraction widely. In section IIII we tend to focus on completely different power improvement techniques. In section IV we tend to given the advanced power recovery technique and in section V we tend to terminate the choice of various techniques for various approaches.
2. Need for Low Power Design
Power dissipation is one among the leading and limiting factors in planning low power moveable devices and increasing power consumption levels in integrated circuits have become a serious issue of the semiconductor business. The demand for low power moveable devices that consume low power is increasing day by day. restricted battery life, higher in operation frequency, increased chip density, and packaging issues are some main factors that cause the researchers to shift their minds from high speed to low power style. Some main factors for this diversion are represented in brief within the below- mentioned subsections.
A. Performance Requirement
In the current schema, moveable devices are requiring high system performance with terribly low power dissipation, like mobiles, laptops, and personal digital assistants (PDAs).
B. Increased Chip Density
High chip density with high performance has additionally forced to VLSI designers to design high-density circuits. But, with the rise within the chip density, the quantity of transistors fabricated on an equivalent chip has been enhanced that causes the entire capacitance to be enhanced. Consequently, power consumption is enhanced because it is directly proportional to the overall capacitance of the circuit [22]. Devices with high performance and turnout want high operational frequency, that once more will increase the power consumption as a result of power consumption is directly proportional to the operational frequency. This creates a good challenge for the designers to take care of the trade-off between power consumption and system performance.
C. Battery Power Limitations
As all of the portable devices are power-driven by the battery and, with the increasing demand for moveable devices the demand for big backup with a long battery, with less weight has been raised currently. recent Nickel-metal (Ni-Cd) batteries have already been replaced by high energy density (energy hold on per unit weight) Nickel Metal-Hydride (Ni-MH) and Lithium-Ion batteries [23]. However, a revolutionary increase within the battery capability can't be expected shortly as a result of it's already been reached to the severe level explosive chemicals, and client safety is given a priority at now. It concludes that battery imposes a robust limit on the low power VLSI design and increasing the battery capacity cannot come back below the class of low power circuit design, as battery design itself desires special attention towards it.
D. Packaging Technology
The packaging drawback is another major difficult issue for superior microprocessors wherever it becomes necessary to mount a cooling fan directly on the chip.
3. Sources of Power Dissipation
Power dissipation in CMOS circuits [24] are often divided into 2 categories: Dynamic power consumption and Static power consumption i.e.,
Leakage Power Figure 1: Major sources of power dissipation in CMOS circuits
A. Dynamic Power
There are 3 main parts of dynamic power dissipation. 1st is switching power second is short circuit power and therefore the third is power consumption because of unwanted glitches available in digital circuits. Vdd
Pdynamic ^ Pswitching ^ Pshortcircuit ^ Pglitching
Vdd (2) Vin=LOW Icharging CL Vout Vin= HIGH^ Vout CL (a) (b) Figure2: Basic CMOS inverter, (a) charging mode and (b) discharging mode
B. Switching Power
The dynamic power consumption occurred because of the shifting [22] activities of the logical inputs from logic HIGH to LOW or vice-versa. All logical switching activities give the base for internal capacitive nodes to either charge from 0V to Vdd through a pull-up network or to discharge the nodes from Vdd to ground through a pull-down network. This charging and discharging action are shown in Short Circuit Power Short Circuit Powersss Glitching Power Switching Power Idischarging Dynamic Static Power Power Dissipation in CMOS Circuits
dd the figure by use of exploitation basic CMOS inverter. Charging activity draws current from the power supply, whereas discharging action flows current from node to ground and thus the power is consumed. This power is dissipated within the charging and discharging resistor (parasitic or purposely fabricated) within the kind of heat. the common power being delivered by charging and discharging circuit is given by
P CV^2 f (3)
Where, C = Node capacitance (parasitic or intentionally fabricated capacitive load), Vdd = Supply voltage, f = charging and discharging frequency.
C. Short Circuit Power
When the input voltage of CMOS inverter is bigger than Vthn of NMOS then, the NMOS transistor is going to be in ON state and once the input voltage is a smaller amount than (Vdd - Vth)) then, PMOS transistor is going to be in ON state. short circuit power in CMOS circuits represents the power consumed throughout a condition within which each PMOS and NMOS logic is in ON state. once input switches (from LOW to HIGH or vice versa), there's a short period that input level lies between Vthn and (Vdd - Vthp) and each transistor turned ON. a short circuit path is established between Vdd and ground so, short circuit current can flow that causes power consumption. The short circuit power is given by [25]
Pshortcircuit =
( V^ dd −^2 V^ th )
T p
Where β is transistor coefficient, τ is rise/fall delay and Tp is the period of the input waveform.
D. Glitching Power
The glitching power [26-27] is another type of dynamic power consumption, which has both power consumption because of switching and power consumption because of a short circuit. Power consumption because of glitch usually happens when the output of a logic circuit changes momentarily changes its state before going into a steady state. this can be a condition that happens when more than 2 inputs have modified their state. as an example in figure three, if input changes from “111” to “010”, output jumps to logic HIGH for an instant then return to the logic LOW level. The presence of flaw at the output is the result of unequal rise and fall delay of logic gates at a distinct level. the matter of flaw is often resolved by applying correct logic optimization technique to the circuit i.e., by latching the outputs and synchronized it with a clock signal, so inputs to successive block are synchronized. The glitching power is given by
Pglitch = V dd
2
CL f glitch ( 5 )
V θ =
KT
q
n is that the sub-threshold swing constant, Vbs0, Vgs0, Vds0, and Vth0 are the majority to supply voltage, the gate to source voltage, and drain to source voltage and threshold voltage, respectively. γ is that the body bias effect coefficient and η is that the Drain induced Barrier Lowering (DIBL) constant. The above equation shows that sub-threshold leakage current exponentially depends on Vgs0, Vds0, and Vth0. Sub-threshold leakage is a major source of leakage power dissipation in nanoscale MOS devices.
G. Gate Leakage
Gate leakage current is because of the direct tunneling of electrons or holes from the substrate to the gate terminal. This direct tunneling is modeled in [33-34] as gate direct tunneling current density (JDT) and is given by J (^) DT = A (^) ( V (^) ox / T (^) ox ) 2
exp(
− B (^) ( 1 −( 1 − V (^) ox / φox )
)
V ox / Tox )^
Where,
B =
8 π √ 2 m
¿
3 qK
m*^ is the effective mass of an electron, Vox is the potential drop across thin oxide, Фox is the barrier height of the tunneling electron and Tox is the oxide thickness.
4. POWER MANAGEMENT LEVELS
Effective power management involves the choice of the proper technology, the utilization of optimized libraries, IP (intellectual property), and design methodology [35]. we survey state-of-art optimization strategies at completely different abstraction levels. Inventory Management), POS (Point of Service), ReSA (Retail Sales Audit), and RIB (Retail Integration Bus).
A. Technology Level
Proper technology choice is one of the key aspects of power management [35]. The goal of every technological advancement is to enhance performance, density, and power consumption more generalized type of scaling is used.
I. Using Multi-threshold Voltage
Multi-threshold CMOS (MTCMOS) is a way to cut standby leakage current in the circuit, with the utilization of a high threshold apply to the MOS device to decouple the logic either from the supply or ground during long idle periods, or sleep states. Figure five shows an MTCMOS circuit, wherever the logic block is built using low threshold devices, and also the Power/ground supply given to the gate of the MTCOMS is a gated by high threshold header/footer switch[36]. Figure 5: MTCMOS Circuit
II. Multi-supply Voltage (Voltage Islands)
Multi-Vdd is an efficient methodology to decrease both leakage and dynamic power, by assignment completely different provide voltages to cells according to their timing criticality. in the multi-Vdd design, cells of various supply voltage are usually grouped into a small range of voltage islands (each having one supply voltage), to avoid complicated power supply system and an excessive quantity of level shifters. A low power design methodology that manages power, timing, and design price by using multi-Vdd and voltage islands should be developed [36][37].
B. Circuit Level
Transistor Sizing: The length-to-width ratio of transistors determines the driving strength and speed. On upsizing, gate delay decreases, however, the power dissipated within the gate will increase. Further, the delay of the fan-in gates will increase due to raised load capacitance. Given a delay constraint, finding an applicable size of transistors that minimizes power dissipation could be a computationally tough drawback. A typical approach to the matter is to calculate the slack at every gate in the circuit, wherever the slack of a gate corresponds to how much the gate can be delayed while not effecting the critical delay of the circuit.
C. Logic Level
We survey optimizations that cut switching activity power of logic-level combinatory and ordered circuits in- this section.
I. Combinational
Combinational logic optimization has traditionally been decomposed into 2 phases: technology- independent optimization and technology-dependent optimization. within the first phase, logic equations are manipulated to cut space, delay, or power dissipation. in the second part, the equations are mapped to a specific technology library using technology mapping algorithms, once more optimizing for combinational, delay, or power. For a comprehensive treatment of combinational logic synthesis ways targeting space and delay [38]. Don’t-care Optimization: Any gate in a combinational circuit has associated controllability and observability don’t-care set. The controllability doesn't-care set corresponds to the input combos that
iv. Pin Swapping
Some cells will have input pins that are symmetrical to the logic function (for example, in a 2-input NAND logic gate the 2 input pins are symmetric) however have different capacitance values. Power may be reduced by assigning a better switching rate net to a lower capacitance pin Power minimization techniques like pin swapping is additionally referred to as local transformations [51]. they're applied on gate netlists and concentrate on nets with large switched capacitance. Example: think about the four- input logic gate with totally different capacitance values at the pin. a high activity net is connected to the pin no four that's pin “d” that has the minimum input capacitance. to attain the minimum input capacitance pin swapping is completed between the pins “a” and “d”.
v. Power Shutoff or Power Gating
Power gating is that the technique accustomed temporarily shut down the sub-blocks to scale back the overall leakage power of the chip. This temporary closing time call decision a “low power mode” or “inactive mode”. once circuit blocks are needed for operation another time they're activated to “active mode". These 2 modes are switched at a suitable time and in a very suitable manner to maximize power performance whereas minimizing impact to performance. This goal of power gating is to reduce leakage power by temporarily cutting power off to selective blocks that aren't needed in this mode.
D. Architectural and Behavioural level
i. Memory Splitting
Off-chip memory accesses are pricy power-wise. rearrangement of bus transactions (to minimize signal transitions) will reduce overall energy consumption. the amount of bit flips on the memory bus may be reduced by correct data encoding or by scheduling bus transactions within the order during which they might cause the lowest signal changes.
ii. Operand Isolation
Redundant operations are identified and special isolation circuitry is used to stop switching activity from propagating into a module whenever it's getting ready to perform a redundant operation.
E. System and Software Level
An increasing fraction of applications are being implemented as embedded systems consisting of hardware and software system parts. As a serious part of the functionality is within the variety of instructions as opposed to gates, Hardware-based power estimation and optimization approaches aren't fully applicable here. This motivates the necessity to think about the power consumption in microprocessors from the purpose of the software. Instruction-level power models are developed with success for a few business CPUs. Given the flexibility to judge programs in terms of power/energy prices, it's possible to look at the design space in software power optimization. the selection of the algorithmic program used will impact the power value since it determines the runtime complexity of a program. This issue is explored in [49]. it's been noted that the order of directions can even have a bearing on power since it determines the internal switching in the C.P.U. CAD Methodologies and Technique: Today's EDA tools effectively support these power- management techniques [50]. They additionally give extra power savings throughout implementation. Low power VLSI designs are achieved at varying levels of the design abstraction from algorithmic and system levels right down to layout and circuit levels.
5. POWER OPTIMIZATION TECHNIQUES
A. Static Power Reduction Techniques
There are various leakage power reduction techniques supported modes of operation of systems. The two operational modes are a) active mode and b) standby (or) idle mode. To minimize this power, technology scaling, voltage scaling, clock frequency scaling, reduction of switching activity, etc., were widely used.
i. Multi-Vth optimization/ (Multi Threshold -MTCMOS):
P. Sreenivasulu et al [10] discussed that MTCMOS (Multiple Threshold CMOS) could be an effective technique in reducing leakage currents within the standby mode. This method utilizes a transistor with multiple threshold voltages(Vth) to optimize power and delay. Here low voltage devices were utilized in important delay methods to minimize clock periods. Higher voltage devices were used on non- important methods to scale back static leakage power without incurring a delayed penalty. Fig.6 MTCMO technique He additionally mentioned that this system reduces many orders of magnitude reduction in leakage power through two effects. First. if the original CMOS circuit effective leakage width is reduced to the width of the single “off” NMOS Transistor second the increase in an exponential reduction in leakage power can be achieved because of the enlarged threshold voltage. in this, if the sleep transistor is turned off more strongly further reduction in leakage can be achieved.
ii. Transistor Stacking
Narendra et al, [11] showed the stacking of two OFF transistors that considerably scale back sub- threshold leakage compared to a single OFF transistor. It is an effective way to reduce leakage power in active mode. The transistor stacking technique uses the dependence of I sub on the source terminal voltage Vs. With the increase of Vs of the transistor, the subthreshold leakage current reduces exponentially. If natural stacking of transistors does not exist in a circuit, then to utilize the stacking effect a single transistor of width W is replaced by two transistors each of width W/2. This is called forced stacking as shown in Figure 7.
J.C. Park et al, [12] described a sleepy stack technique that mixes the sleep transistor approach throughout active mode and therefore the stack approach throughout standby mode. during this technique, forced stacking is first implemented. Then too at least one of the stacked transistors, an asleep transistor is inserted in parallel. Thus, throughout the active mode, the sleep transistors are on thereby reducing the effective resistance of the path. This ends up in reduced propagation delay throughout active mode as compared to the forced stacking method. throughout standby mode, the sleep transistor is turned off and the stacked transistor suppresses the leakage power. Figure 8 shows the circuit of a sleepy stack inverter, where the S and S’ are sleep control signals. Fig.8 sleepy stack inverter circuit
i. Sleepy Keeper Approach
Ajay Kumar dadoria et al [13] planned a sleepyheaded keeper approach. during this approach, two extra transistors are used in parallel with sleep transistors Over the pull-up network, we tend to ar victimization the MOS transistor that is driven by the feedback of the output circuit and PMOS transistor within the pull-down network. In this [13] technique two transistors are connected in parallel with sleep transistors. on top of the pull-up network, the NMOS transistor is employed. This input is given from the feedback of the output circuit. PMOS is employed in a very pull-down network. It maintains correct output logic. Since it's a victimization feedback technique and here we will use higher Vth transistors for any reduction of static power.
Fig.9. Two input NAND gate with sleepy keeper technique [13] Then Ajay Kumar dadoria et al[13] proposed a Modified galeor with sleepy with low and high Vth transistors. during this the modifications ar the gate of NMOS and PMOS galeor transistor has been connected to the drain rather than victimization low Vth NMOS galeor transistors, high Vth transistors are used during this approach, correct voltage swing is achieved by dynamic the position if inputs of galeor transistors and applying a high threshold to sleep transistors. This advantage achieved by this method. Fig.10 NAND gate with galeor with a sleepy approach
ii. Lector approach
Narender Hanchate et al, [14] proposed a novel technique referred to as the selector (Refer Fig.
- for reducing discharge power in CMOS circuits. He introduced two leakage control transistors(LCT) a PMOS and NMOS inside the gate. The gate terminal of every LCT is controlled by the supply of the opposite. during this arrangement, one in every of the LCT’s is usually close to its discontinue voltage for any input combination. This will increase the resistance of the trail from Vdd to ground resulting in a major decrease in discharge currents. this method works effectively in each active and idle states of the circuit, resulting in better leakage reduction. The experimental results indicate an average leakage reduction of 79.4% for MCNC “91benchmark circuits.
The power is saved in much the way that if the target device clock is ON the controlling device's clock is OFF and vice versa in this technique the clock and dynamic power is saved during the negative edge of the clock as this technique is designed for the positive edge. this method by implementing synchronous circuits power is concentrated to twenty and additionally reduces the hardware complexness.
ii. Dual VDD
Sai Sri Harsha [17] discussed A Dual VDD Configuration Logic Block and a Dual VDD routing matrix is shown in figure 8. In this technique, the supply voltage to the logic and routing blocks are programmed to reduce power consumption. it can be done by assigning low-VDD to non-critical paths in the design however whenever 2 different provide voltages co-exist, static current flows at the interface of the VDDL half, and therefore the VDDH half. Level converters are accustomed upconvert a coffee VDD to a high VDD. Fig.8 Dual VDD architecture [16]
iii. Clustered Voltage Scaling (CVS)
Siva Kumar et al [18] mentioned that this method power may be optimized while not compromising circuit performance by creating the use of 2 supply voltages. Gates within the important path are run at the lower supply, as shown in Fig. 9. to reduce the amount of interfacing level converters required, the circuits that operate at reduced voltages are clustered resulting in clustered scaling. Here just one voltage transition is allowed on a path and level conversion takes place only at flip- flops.
Fig 9. Cluster Structure [18]
iv. Dynamic Voltage and Frequency Scaling (DVFS)
Siva Kumar et al [18] mentioned that several circuits have time-varying performance needs in such cases the power is saved by reducing the clock frequency to a sufficient level to complete the task on schedule then reducing the voltage to that level. this can be referred to as dynamic voltage frequency scaling (DVFS). Fig.10 shows the DVFS technique to avoid wasting power. this method is enforced by a correct controlling program[18]. Fig.10 DVFS technique [18]
v. Adaptive Voltage Scaling (AVS)
This is an extension of DVFS wherever the control loop is used to regulate voltage and frequency for a dynamical workload. [18]. The AVS loop regulates method or performance by automatically adjusting the output voltage of the power offer to compensate for process and temperature variation within the processor [18]. compared to open-loop voltage scaling solutions like Dynamic Voltage Scaling (DVS), AVS uses up to forty fifths less energy as shown in Fig11. AVS could be a system-level scheme that has elements in both the processor and power supply.
Some partially adiabatic logic families are: -
- Efficient Charge Recovery Logic (ECRL)
- 2N-2N2P Adiabatic Logic
- Positive Feedback Adiabatic Logic (PFAL)
- Clocked Adiabatic Logic
ii. Fully Adiabatic
In totally adiabatic circuits, all the charges on the load capacitance get recovered and feedback to the power supply. due to that adiabatic circuits become slower and sophisticated as compared to partial adiabatic circuits [20]. Some fully adiabatic logic families are: -
- Pass Transistor Adiabatic Logic (PAL)
- Two-Phase Adiabatic Static CMOS Logic (2PASCAL)
- Split-Rail Charge Recovery Logic (SCRL). Yet some complexities in adiabatic logic design bear on. two such complexities, for instance, are circuit implementation for time-varying power sources that require to be done and computational implementation by low overhead circuit structures has to be followed. There are two huge challenges of energy recovery circuits; 1st, slowness in terms of today’s standards, second it needs ~50% off additional space than standard CMOS and simple circuit style.
Fig.13 Variation of power dissipation with frequency for different full-adder circuits using different adiabatic logic [21] Fig .13 shows the comparison of the performance of different adiabatic logic adder circuits with traditional CMOS adder circuits for different full adder circuits. Y.sunil Gavaskar reddy et al[21] implemented and their analysis shows that designs based on the adiabatic principle give superior performance when compared to traditional approaches in terms of power even though their. transistor count is high in some circuits. So for low power and ultra-low power requirements, adiabatic logic is an effective alternative for traditional CMOS logic circuit design.
7. CONCLUSION
In this paper, we presented various power optimization techniques almost in all levels of design. It can be concluded that the important performance parameters such as dynamic power, leakage power, propagation delay, and therefore the PDP square measure powerfully reticulate. Table.1 Advantages and Disadvantages of Power Optimization Techniques Technique Advantage s Disadvantages MTCMOS [10] Power-efficient with no effect on speed More area Transistor Stacking [11] Easy to implement, leakage saving, easy to Fabricate Propagation delay increases Sleepy stack [12] Single threshold transistors, less delay compared to transistor stacking Needs to control circuits, area increases, low power savings LECTOR [14] A control circuit is not required. Best power savings in both the modes of operation Delay increases Body bias [15] More power savings Complexity in implementation Clock gating [16] Medium power savings, less effect on speed Complexity in implementation Dual Vdd [17] Medium power savings Effects on speed, control circuitry is required DVFS [18] More power savings Complexity in implementation Adaptive voltage scaling [18] Efficient in power savings, Improves performance compared to DVFS. Effects in speed Adiabatic [21] More power savings More area
