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(19) United States
US 20120268.093A
(12) Patent Application Publication (10) Pub. No.: US 2012/0268093 A
YAMADA (43) Pub. Date: Oct. 25, 2012
(54) DC-DC CONVERTER CONTROL METHOD
AND DC-DC CONVERTER CONTROL CIRCUIT
(75) Inventor: Kouhei YAMADA, Matsumoto-city (JP)
(73) Assignee: FUJI ELECTRIC CO.,LTD., Kawasaki-shi (JP)
(21) Appl. No.: 13/455,
(22) Filed: Apr. 25, 2012
(30) Foreign Application Priority Data
Apr. 25, 2011 (JP) ................................. 2011-
110 120 124 121
Publication Classification
(51) Int. Cl. GOSF I/56 (2006.01) HO3K 7/08 (2006.01) (52) U.S. Cl. ......................................... 323/283; 327/ (57) ABSTRACT
The transient response of an output Voltage to a load fluctua tion is improved, in a Switching power source that carries out a PWM control. In a DC-DC converter wherein a switching element of an output stage is controlled by a drive signal, whose pulse width is set at a minimum value, output from a PWM signal generating circuit based on an output Voltage output from an error amplifier in accordance with the differ ence between a feedback Voltage in accordance with an out put Voltage of the output stage and a reference Voltage, there is provided a minimum pulse width detector circuit that Sup plies a current to a phase compensation capacitor when the pulse width of the drive signal is at the minimum value, thus preventing the output Voltage from dropping below a value corresponding to the minimum value when the load fluctu ates, and improving transient response characteristics of the output Voltage.
W D Ea W-PWM Wawm dry W2 CLR (b
W D2 (Tmin)
Delay W (Ts) D
135 134
Patent Application Publication Oct. 25, 2012 Sheet 1 of 4 US 2012/0268093 A
AupA
Patent Application Publication Oct. 25, 2012 Sheet 3 of 4 US 2012/0268093 A
FIG.
Vpwm
Vdrv
Worv
V
V
(CLR)
W
V
(132 GATE VOLTAGE)
lup
When Tp > Tmin When Tp K. Tmin
Patent Application Publication Oct. 25, 2012 Sheet 4 of 4 US 2012/0268093 A
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US 2012/0268.093 A
including: setting a non-zero minimum value for the pulse width of the output signal of the PWM signal generating circuit; and Supplying a current to the phase compensation capacitor, based at least partly on the pulse width of the output signal acting at (e.g., having) the non-zero minimum value.
- A second aspect of the invention provides a DC-DC converter control circuit including an error amplifier that amplifies and outputs the difference in voltage between a feedback Voltage output from an output stage and a reference Voltage, a phase compensation capacitor connected to an output side of the error amplifier, and a PWM signal gener ating circuit that carries out a pulse width modulation (PWM) changing the pulse width of an output signal for a Switching element of the output stage in accordance with the output voltage of the error amplifier, wherein the PWM signal gen erating circuit includes a minimum pulse width setting circuit that sets a non-zero minimum value of the pulse width of the output signal for the Switching element, and a minimum pulse width detector circuit that supplies a current to the phase compensation capacitor based at least partly on the pulse width of the output signal acting at (e.g., having) the non-Zero minimum value.
- According to the invention, it is possible to provide a technology whereby it is possible to realize an improvement in the transient response of an output Voltage to a load fluc tuation, or the like, in a Switching power source that carries out a PWM control.
BRIEF DESCRIPTION OF THE DRAWINGS
0020 FIG. 1 is a diagram showing one example of a con figuration of a DC-DC converter control circuit, which is one embodiment according to a control method and control cir cuit of the invention; 0021 FIG. 2 is a diagram showing in further detail one portion of the configuration of the DC-DC converter control circuit of FIG. 1, which is one embodiment according to the control method and control circuit of the invention; 0022 FIG. 3 is a timing chart showing one example of an action of the DC-DC converter control circuit, which is one embodiment according to the control method and control circuit of the invention; and 0023 FIG. 4 is a circuit diagram of a DC-DC converter of reference technology of the invention.
DETAILED DESCRIPTION OF THE EMBODIMENTS
- In this embodiment, as one mode, a switching power source that carries out a PWM control is such that current is Supplied to a phase compensation capacitor when the pulse width of the PWM control is at a minimum value, thus pre venting a drop in the output Voltage of an error amplifier. 0025 Because of this, it is possible to prevent the output voltage of the error amplifier dropping beyond the lower limit of a PWM signal control range, thus achieving an improve ment in transient response.
- Hereafter, a detailed description will be given, while referring to the drawings, of the embodiment of the invention. 0027 FIG. 1 is a diagram showing one example of a con figuration of a DC-DC converter control circuit, which is one embodiment according to a control method and control cir cuit of the invention.
0028 FIG. 2 is a diagram showing in further detail one portion of the configuration of the DC-DC converter control
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circuit of FIG. 1, which is one embodiment according to the control method and control circuit of the invention. 0029 FIG. 3 is a timing chart showing one example of an action of the DC-DC converter control circuit implementing the control method, which is one embodiment of the inven tion.
- A DC-DC converter M including a PWM signal generating circuit 110 of the embodiment shown in FIG. 1 differs from the reference technology of FIG. 4 in that a Tmin detector circuit is provided in the PWM signal generating circuit, and a current up is Supplied to a phase compensation capacitor CC when the pulse width is Tmin (that is, when the pulse width becomes smaller than Tmin in the event that a minimum pulse width Tmin is not provided).
- As shown in FIG. 1, the DC-DC converter M of the embodiment includes an output stage 200 comprising a switching element 210 (SW), direct current power source 250, inductor 220 (L), commutating diode 230 (D), and capacitor 240 (C), and a control circuit 100 for controlling a turning on and off of the switching element 210 of the output stage 200.
- In the case of the DC-DC converter M of the embodiment, the switching element 210 and inductor 220 of the output stage 200 are connected in series with a load, configuring a buck converter, reduce the direct current Volt age of the direct current power source 250, and output it to an output terminal 260.
- Also, the control circuit 100 includes the PWM
signal generating circuit 110, an error amplifier 150 including
a transconductance amplifier, and a phase compensation capacitor 160 (CC).
- The switching element 210 of the output stage 200, controlled on and off by a drive signal VdrV output from the PWM signal generating circuit 110, by opening and closing a connection path between the direct current power source 250 and the inductor 220, commutating diode 230, and capacitor 240, outputs a direct current output Voltage Vout in accor dance with the ratio between the path being open and closed to the output terminal 260. 0035 Also, the output voltage Vout becomes a feedback voltage Vd of the error amplifier 150 via a voltage dividing resistor 140.
- The error amplifier 150 amplifies the difference between a predetermined reference voltage Vrefand the feed back voltage Vd, which is the output voltage Vout of the output stage 200 divided and fed back by the voltage dividing resistor 140, and outputs an output voltage Vea to PWM signal generating circuit 110. More specifically, by injecting or discharging a current in accordance with the difference between the reference voltage Vref and feedback voltage Vd into or from the phase compensation capacitor Ce, the output voltage Vea, wherein the difference between the reference voltage Vref and feedback voltage Vd is amplified, is gener ated as the Voltage of the phase compensation capacitor Ce.
- Then, in the case of the embodiment, the PWM signal generating circuit 110 of the control circuit 100 includes a minimum pulse width detector circuit 130, to be described hereafter, wherein the minimum pulse width detec tor circuit 130 can supply the current Iup to the phase com pensation capacitor CC of the error amplifier 150 at a kind of timing to be described hereafter. 0038 Next, referring to FIG. 2, one example of an internal configuration of the PWM signal generating circuit 110 con
US 2012/0268.093 A
figuring the control circuit 100 of the DC-DC converter M of the embodiment will be described in further detail.
- The PWM signal generating circuit 110 configuring the control circuit 100 of the embodiment includes a PWM
converter 111, which converts the output voltage Vea of the error amplifier 150 into a PWM original signal (pulse width modulated original signal) Vpwm, and a minimum pulse width setting circuit 120 and the minimum pulse width detec tor circuit 130 as a circuit that, when the pulse width of the PWM original signal Vpwm is smaller than the minimum value Tmin, sets the minimum value Tmin by extending the pulse width, and injects current into the phase compensation capacitor Ce.
- Herein, as the PWM original signal Vpwm output from the PWM converter 111 is a signal for which the mini mum value Tmin, which is the minimum on time, has not yet been set, the minimum value thereof is zero. Specifically, the PWM original signal Vpwm, being a signal generated by comparing the output Voltage (error signal) Vea of the error amplifier 150 and an unshown carrier signal Vcary formed of a triangular wave or sawtooth wave, is a signal that is at a high level when Vead-Vcary.
- When the output voltage Vea of the error amplifier 150 is lower than the minimum value of Vcary, the PWM original signal Vpwm remains at a low level, and the on time is Zero.
- The minimum pulse width setting circuit 120 includes a delay circuit 123 (D2), whose fall delay time is the
minimum value Tmin, a D flip-flop 121 (D-FF) having an
asynchronous reset function, and a NOR (negative logical Sum) gate 122.
- The delay circuit 123 (D2) with the fall delay time Tmin, being a circuit that delays only the leading edge (fall) of an input (in this case, an inverse signal of the drive signal VdrV), is a circuit that does not delay a rise. The delay time Tmin of the delay circuit 123 (D2) corresponds to the mini mum pulse width (minimum value Tmin).
- Then, a D input of the D-FF is fixed at a high level by a fixed input 124, and by resetting the D-FF by an output Q of the D-FF being set at a high level by the rising edge of the PWM original signal Vpwm (Qb, the inverse of Q, is at a low level, which is the inverse logic of VdrV), and a voltage V indicating the later of the fall of an output V1 of the delay circuit 123 (D2) and the fall of the PWM original signal Vpwm being a CLR input of the D-FF, it is possible to realize an on-off action controlling the switching element 210 with the drive signal VdrV, whose pulse width is of a value in accordance with the output Voltage Vea, and which has the minimum value Tmin.
- Furthermore, in the case of the embodiment, the minimum pulse width detector circuit 130 that controls the current Iup of the PWM signal generating circuit 110 includes a fall delay circuit 135 (D1) that delays the trailing edge (the fall) of Vpwm by a short time (ofan extent slightly longer than the delay time of a logic gate of the D-FF, and the like, of the minimum pulse width setting circuit 120), an inverter 134 that inverts the output of the delay circuit 135 (D1), a NAND (negative logical product) gate 133 that obtains the inverse of the logical product of an output V3 of the inverter 134 and the drive signal VdrV, and a P-channel MOSFET 132 that con ducts in accordance with the output of the NAND gate 133, outputting the current.
- Then, the P-channel MOSFET 132 controls a turn ing on and off of an action charging the phase compensation
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capacitor 160 (Ce) with the current Iup by turning on and off a fixed current from a fixed current source 131. 0047 Next, referring to FIG.3 and the like, a description will be given of one example of a working of the control circuit including the PWM signal generating circuit 110, error amplifier 150, phase compensation capacitor 160, voltage dividing resistor 140, and the like, in the DC-DC converter M of the embodiment.
- In the PWM signal generating circuit 110, when a pulse width Tp of the PWM original signal Vpwm output from the PWM converter 111 is larger than the predetermined minimum value Tmin (the left half of FIG. 3), the output V of the delay circuit 123 (D2) is already at a low level at a point at which Vpwm changes to a low level, meaning that the voltage V2 changes to a high level, the D-FF is reset, and the drive signal VdrV, which is the output of the PWM signal generating circuit 110, immediately changes to a low level owing to the delay of the logic gate of the D-FF and the like.
- Because of this, it does not happen in the minimum pulse width detector circuit 130 that a signal (the output V3) wherein Vpwm is delayed and inverted by the delay circuit 135 (D1) and the drive signal VdrV are both at a high level, the P-channel MOSFET 132 does not conduct (come on), and no charging of the phase compensation capacitor 160 (CC) with the current Iup is carried out.
- Meanwhile, when the pulse width Tp of Vpwm is smaller than the minimum value Tmin (the right half of FIG. 3), the drive signal VdrV does not change to a low level until
the output V1 of the delay circuit 123 (D2) in the minimum
pulse width setting circuit 120 changes to a low level (that is, until the voltage V2, which is the reset input (CLR) of the D-FF, changes to a high level), even when Vpwm changes to a low level.
- Then, on a time Tmin elapsing from Vpwm rising, the D-FF is reset by the output V1 of the delay circuit 123 (D2) changing to a low level, and the drive signal VdrV changes to a low level. Consequently, when the pulse width Tp of Vpwm is smaller than the minimum value Tmin, the drive signal Vdrv always maintains a high level for the period of the minimum value Tmin. That is, the minimum pulse width Tmin is set for the drive signal VdrV. 0.052 Because of this, when the pulse width Tp of Vpwm is Smaller than the minimum pulse Tmin of the drive signal Vdrv, the P-channel MOSFET 132 conducts for a period At until the drive signal VdrV changes to a low level (that is, for a period in which a pulse width H of the drive signal Vdrv is extended to the minimum value Tmin), and the current Iup is Supplied to the phase compensation capacitor 160 Ce. 0053 As a result of this, the output voltage Vea of the error amplifier 150 no longer drops below a voltage at which the pulse width of Vpwm becomes the minimum value Tmin. 0054 Because of this, when there is an increase in the pulse width of the drive signal Vdrv needed due to an increase in the load current, it is possible to minimize the increase in width when the output voltage Vea of the error amplifier 150 increases to a commensurate value, and to keep the time needed for this to a minimum, and thus possible to keep the drop in the output voltage Vout of the DC-DC converter M to a minimum.
- Because of this, for example, it is possible to sup press a fluctuation in output Voltage when the load connected to the output terminal 260 of the DC-DC converter M tran siently fluctuates widely.
US 2012/0268.093 A
detector circuit coupled to an output of the minimum pulse width setting circuit, and configured to, based at least partly on the output of the minimum pulse width setting circuit, output a current.
- The control circuit of claim 10, further comprising a capacitor coupled to the minimum pulse width detector cir cuit at a node that outputs the current.
- The control circuit of claim 8, further comprising an error amplifier coupled to the PWM signal generating circuit and outputting an amplified difference signal, the difference signal corresponding to a difference between a feedback Volt age output from an output stage of the control circuit and a reference Voltage.
- The control circuit of claim 12, further comprising a PWM converter configured to convert the amplified differ ence signal into a pulse width modulated signal, at least one pulse of the pulse width modulated signal corresponding to
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the input pulse of the PWM signal generating circuit having the pulse width smaller than the predetermined minimum value.
- The control circuit of claim 12, the PWM signal gen erating circuit further configured to generate a drive signal, the drive signal including the output pulse extended to have the predetermined minimum value, wherein the drive signal is coupled to a Switching element configured to control the Output Stage.
- The control circuit of claim 10, the minimum pulse width detector circuit comprising a Switching device config ured to turn a fixed current from a fixed current source on and off to output the current.
- The control circuit of claim 15, wherein the switching device is configured to turn the fixed current on and off based at least partly on a drive signal output by the minimum pulse width setting circuit, the drive signal including the output pulse extended to have the predetermined minimum value. c c c c c
