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Main points of this past exam are: Negative Value, Representations and Arithmetic, Most Negative Value, Representations Below, Signed Representations, Between Sequential Values, Decimal Notation, Compute the Operations, Numbers Are Expressed, Overflow Occurs Assuming
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4 problems, 5 pages Exam Two 22 October 2003
Instructions: This is a closed book, closed note exam. Calculators are not permitted. If you have a question, raise your hand and I will come to you. Please work the exam in pencil and do not separate the pages of the exam. For maximum credit, show your work. Good Luck!
Your Name ( please print ) ________________________________________________
1 2 3 4 total
4 problems, 5 pages Exam Two 22 October 2003
Problem 1 (3 parts, 32 points) Representations and Arithmetic
Part A (15 points) For the 24 bit representations below, determine the most negative value, most positive value, and step size (difference between sequential values). All answers should be expressed in decimal notation. Fractions (e.g., 3/16ths) may be used. All signed representations are two’s complement.
representation most negative value most positive value step size
signed integer (24 bits). (0 bits) unsigned fixed-point (12 bits). (12 bits) unsigned fixed-point (16 bits). (8 bits) signed fixed-point (16 bits). (8 bits)
Part B (8 points) For each problem below, compute the operations using the rules of arithmetic, and indicate whether an overflow occurs assuming all numbers are expressed using a six bit two’s complement fixed-point representation.
result
signed error?
Part C (9 points) Answer the following questions for the single precision floating point representation discussed in class (1 sign bit, 23 mantissa bits, 8 exponent bits).
range of mantissa values (in decimal): to
largest represented value (power of two): 2 ________
approx. number of decimal significant figures:
4 problems, 5 pages Exam Two 22 October 2003
Problem 3 (3 parts, 24 points) More ways to implement state
Part A (8 points) Implement a transparent latch using only two-input NAND gates. Label the inputs In and En , and the output Out.
Part B (8 points) Implement a register with read and write enable using transparent latches, pass gates, and inverters. Use an icon for the transparent latches. Label the inputs In , WE, RE, Φ 1 , Φ 2 and the output Out.
Part C (8 points) Assume the following signals are applied to your register. Draw the output signal Out. Draw a vertical line where In is sampled. Assume Out starts at zero.
4 problems, 5 pages Exam Two 22 October 2003
Problem 4 (3 parts, 23 points) More ways to implement state Part A (5 points) Consider a two bit counter with count enable (CE) and clear (CLR) displaying the flowing timing diagram. Identify the counter type.
It’s a divide by counter. Part B (10 points) Suppose you are given the following incorrect implementation of a counter. Complete the timing diagram below by showing the outputs (O 0 and O 1 ) for clock cycles 7 through 14.
TE Out Clr
TE Out Clr
Ο 1
Ο 0
CE
CLR
Clock Cycle 1 2 3 4 5 6 7 8 9 10 11 12 13 14
Part C (8 points) Design the max count detector needed for a divide by 25 counter. Label all inputs (counter outputs O 0 , O 1 , O 2 …). Don’t include unnecessary inputs.
