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Digital Logic and Sequential Circuits Exercise Solutions, Exams of Digital Systems Design

Solutions to various digital logic and sequential circuits problems. Topics include implementing boolean functions using nand and nor gates, designing finite state machines, and creating counters. Students can use this document as study notes, summaries, or cheat sheets to prepare for exams or assignments.

Typology: Exams

2012/2013

Uploaded on 04/02/2013

sheth_kim55
sheth_kim55 🇮🇳

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Name___________________
SID_____________________
EECS150
Midterm1
2/16/06 Total /100
1) Given F=AB+CD’
a. Implement F using as few 2 input NAND gates as possible. Assume that
only the true literals (A,B,C,D) are available, not their complements (A’,
B’, C’, D’).
b. Write F’ in product of sums notation
2) Given G = (A+B)(C’+D)
a. Implement G using as few 2 input NOR gates as possible. Assume that
only the true literals are available, not their complements.
b. Write G’ in sum of products notation.
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Name___________________

SID_____________________ EECS Midterm 2/16/06 (^) Total /

  1. Given F=AB+CD’ a. Implement F using as few 2 input NAND gates as possible. Assume that only the true literals (A,B,C,D) are available, not their complements (A’, B’, C’, D’).

b. Write F’ in product of sums notation

  1. Given G = (A+B)(C’+D) a. Implement G using as few 2 input NOR gates as possible. Assume that only the true literals are available, not their complements.

b. Write G’ in sum of products notation.

  1. Answer the following questions for the FSM below: a. Is this a Mealy or a Moore machine? b. Briefly describe the function of this sequence detector. When is the output 1?

c. Write a Verilog module which would implement this FSM for input variable “In” and output variable “Out.” Use the same standard format as was presented in the Lab 3 lecture and used in Lab 3. (Define your states; use one always block for next state and output; use one always block for state transition)

  1. Design a counter with one control input. When the input is high, the counter should sequence through three states: 10, 01, 11 and repeat. When the input is low the counter should sequence through the same states in the opposite order 11, 01, 10 and repeat. a. Draw the state diagram and state transition table b. Implement the counter using D flip flops and whatever gates you like. c. Is your counter self-starting with the input either high or low?
  1. [25pts]

Clk

D

G

G

G

G

Q

Q’

1 gate delay

Assume all gates have exactly

the same delay.