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4 problems, 4 pages Exam Three Solutions 21 November 2008
Problem 1 (2 parts, 22 points) Counters
Part A (10 points) Design a toggle cell using two transparent latches, two 2 to 1 muxes, and one inverter. Your toggle cell should have an active high toggle enable input TE , and an active low clear input -Clear , clock inputs Φ 1 and Φ 2 , and an output Out. The - Clear signal has precedence over TE. Label all signals. Also complete the behavior table for the toggle cell.
In Out
En
Latch
In Out
En
Latch
TE
Out
CLR
In Out S
In
In Out S
In
TE -Clear CLK Out
0 0 ↑↓ 0
1 0 ↑↓ (^) 0
0 1 ↑↓ (^) Qo
1 1 ↑↓ (^) -Qo
Part B (12 points) Now combine these toggle cells to build a divide by six counter. Your counter should have an external clear, external count enable, and three count outputs O 2 , O 1 , O 0. Use any basic gates (AND, OR, NAND, NOR, & NOT) you require. Assume clock inputs to the toggle cells are already connected. Your design must support multi-digit systems.
O 0
O 1
O 2
Ext Clr
Ext CE TE Out Clr
TE Out Clr
TE Out Clr
4 problems, 4 pages Exam Three Solutions 21 November 2008
Problem 2 (3 parts, 30 points) Memory Systems
Part A (12 points) Consider a 256 Mbit DRAM chip organized as 32 million addresses of eight bit words. Assume both the DRAM cell and the DRAM chip are square. The column number and offset concatenate to form the memory address. Using the organization approach discussed in class, answer the following questions about the chip. Express all answers in decimal (not powers of two).
number of columns (^) sqrt(2 28 ) = 2 14 = 16K number of words per column (^2 14) / 2^3 = 2^11 = 2K
column decoder required ( n to m ) 14 to 16K type of mux required ( n to m ) 2K to 1 number of address lines in column number 14 number of address lines in column offset (^11)
Part B (10 points) Consider a one gigabyte memory system with 128 million addresses of 8 byte words using a 32 million address by 8 bit word memory DRAM chip.
word address lines for memory system (^) log 2 (128M) = 27 chips needed in one bank (^) 8 bytes x 2 3 bits/byte / 8 bits = 8 banks for memory system (^) 128M / 32M = 2 27 / 2^25 = 4 memory decoder required ( n to m ) (^) 2 to 4 DRAM chips required (^) 8 chips/bank x 4 banks = 32 chips
Part C (8 points) Design a 128 million address by 8 bit memory system with four 64M x 4 memory chips. Label all busses and indicate bit width. Assume R/W is connected and not shown here. Use a bank decoder if necessary.
D D D D
ADDR
CS D D D D
ADDR
CS D D D D
ADDR
CS
ADDR
27
MSEL
D D D D
64M x 4
D D D D
ADDR
CS
64M x 4
64M x 4
64M x 4
D D D D
A25:A0 26
In
Out
En
1 to 2
Out
A
4 problems, 4 pages Exam Three Solutions 21 November 2008
Problem 4 (2 parts, 26 points) Microcode
Using the supplied datapath, write microcode fragments to accomplish the following procedures. Express all values in hexadecimal notation. Use ‘X’ when a value is don’t cared. For maximum credit, complete the description field.
Part A (13 points) (^4 ) 2
R
R R
R −
− ×
= Use only R 1 -R 4 ; modify only R 4.
# X Y Z rwe imen im va auen -a/s enlu lf suen st description
1 2 X 4 1 1 FFFE 0 X 0 X 1 1 R4 <- R2 x 4
2 4 2 4 1 0 X 1 0 0 X 0 X R4 <- R4 + R
3 1 4 4 1 0 X 1 1 0 X 0 X R4 <- R1 – R
(^4 4) X 4 1 1 0001 0 X 0 X 1 1 R4 <- R4 / 2
(^5 4 3 4 1 0) X 1 1 0 X 0 X R4 <- R4 – R
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7
Part B (13 points) Write a microcode sequence that sums three packed ten bit values red, green, and blue of R 1 (format shown below). Assume the most significant two bits of the register are zero. Place the sum of the unpacked red, green, and blue values in R 2. Use only R 1 , R 2 , and R 3 ; modify only R 2 and R 3.
0 0 red blue green 31 30 29 20 19 10 9 0
# X Y Z rwe imen im va auen -a/s luen lf suen st description
1 1 X 2 1 1 03FF 0 X 1 8 0 X R2 <- R1 & 3FF
2 1 X 3 1 1 000A 0 X 0 X 1 0 R3 <- R1 >> 10
3 3 X 3 1 1 03FF 0 X 1 8 0 X R3 <- R3 & 3FF
4 2 3 2 1 0 X 1 0 0 X 0 X R2 <- R2 + R
(^5 1) X 3 1 1 0014 0 X 0 X 1 0 R3 <- R1 >> 20
(^6 2 3 2 1 0) X 1 0 0 X 0 X R2 <- R3 + R
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8
