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A closed book, closed notes test for ece 2030 students in the fall of 2000. The test includes five problems covering topics such as digital logic, switch level circuits, and karnaugh maps. Students are required to write clear answers, show their work, and adhere to the georgia tech academic honor code.
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ECE 2030 Test 1
Fall 2000
Dr. Heck
Write concise, clear answers.
a) Why do we use both n-type and p-type transistors when building circuits to implement digital logic?
n-type and p-type transistor are not ideal switches. n-type is good at pulling low while p-type is good at pulling high. Using both compensates for the nonideal behavior.
b) What is the benefit of using Mixed Logic for gate design?
-easy to analyze and trouble shoot -easy to convert from the one set of gate implementation to another
Suppose F = ( A + B ) C + D ,
a) Create a switch level implementation for F using n-type and p-type transistors. Assume that both the inputs and their complements are available. Your design should contain no shorts and no floats.
F =ABC+D
b) Use mixed logic to create a gate level implementation for F using only NOR gates and inverters. Your design should include the complements of the inputs if they are needed. Determine the number of transistors needed for the design.
Number of transistors for part b) 3 × 4 + 3 × 2 = 18
a) Draw the Karnaugh map for F = ( A + C ) B + AB
b) A truth table is given below. From the truth table, write the SOP and the POS expressions. Then, using a Karnaugh map, express the simplified SOP expression.
Simplified
SOP AD ABD use either
