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4 problems, 6 pages Exam Two Solutions 16 October 2003
Problem 1 (6 parts, 37 points) Numbers and Arithmetic
Part A (4 points) Convert the following hexadecimal values into decimal notation:
hexadecimal notation decimal notation 0x2BF 2x256+11x16+15 = 703
0xF.8 15.
Part B (4 points) Convert the following octal values into hexadecimal notation:
octal notation hexadecimal notation
457263 100101111010110011 2 = 0x25EB
357.4 (^) 011101111.1002 = 0xEF.
Part C (9 points) For each problem below, (a) compute the operations using the rules of addition, (b) indicate whether an error occurs assuming all numbers are expressed using a five bit two’s complement representation, and (c) indicate whether an error occurs assuming all numbers are expressed using a five bit unsigned representation.
addition
result 1 0 0 0 0^ 0 0 0 1 0^ 0 0 0 1 0
signed error? Yes No No
unsigned error? No Yes Yes
4 problems, 6 pages Exam Two Solutions 16 October 2003
Part D (10 points) Convert each subtraction problem (X-Y=Z) below to an addition problem (X+(-Y)=Z) and compute the result of the addition. Also indicate whether an error occurs assuming all numbers are expressed using a five bit two’s complement representation and then indicate whether an error occurs using a five bit unsigned representation.
Result 0 1 1 0 1^ 0 1 1 0 1^ 1 1 1 1 0^ 1 1 1 1 0
Signed Error?
Yes No
Unsigned Error? No (carry out = no borrow out)
Yes (no carry out = borrow out)
Part E (4 points) What is the minimum number of bits needed to represent the following decimal integers in an unsigned integer representation?
a) 45: 6 bits.
b) 128: 8 bits.
Part F (6 points) What is the minimum number of bits needed to represent the following decimal integers in a signed two’s complement integer representation?
a) 128: 9 bits.
b) negative19: 6 bits.
4 problems, 6 pages Exam Two Solutions 16 October 2003
Problem 3 (2 parts, 23 points) Building Blocks
Part A (11 points) Use the decoder below, plus NAND gates to implement a 4-to-1 multiplexer. Clearly label all inputs and outputs. Your NAND gates can have any number of inputs but do not use any other type of gate.
2 to 4
decoder
In 0
In 1
En
Out 0
Out 1
Out^2
Out 3
A
B
C
D
Out
S 0
S 1
Part B (12 points) Each of these circuits use a 2-to-1 Mux to implement a common logic gate or device. Fill in the blanks below with the name of the gate or device that is implemented.
A
out
B
0 OUT
IN 0
S
2 to 1
IN 1
A
out
B
OUT
IN 0
S
2 to 1
IN (^1) in
out
en
OUT
IN 0
S
2 to 1
IN 1
AND XOR Transparent Latch
4 problems, 6 pages Exam Two Solutions 16 October 2003
Problem 4 (2 parts, 25 points) Registers and Timing
Part A (15 points) Consider the register implemented below.
In Out
En
Latch
In Out
En
Latch
mux out
IN s
WE
OUT
A
phi1 phi
Assume the following signals are applied to your register. Draw the signal at point A (output of the first latch) and the output signal Out. Assume A and Out start at zero.
Φ 1
Φ 2
In
WE
Out
A
Part B (10 points) Consider the incorrect implementation of a transparent latch below. Circle the portion of the diagram that is incorrect.
IN OUT
EN
Show the behavior of this latch by completing the OUT column in the truth table below and by drawing the output signal OUT in the timing diagram below.
EN
IN
OUT
IN EN OUT
0 0
0 0
1 1
1 1
Q 0 Q 0
1
0
