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A microprocessor is a programmable integrated device that has computing and decision-making capabilities similar to that of the CPU of a computer.
A microprocessor is a multipurpose, programmable, clock-driven, register-based electronic device that reads binary instructions from a storage device called memory, accepts binary data as input and processes data according to those instructions, and provides results as output.
A microcomputer is a computer that uses a microprocessor as its CPU.
A microcontroller is a devices that has the functionalities of a microprocessor but also has on-chip memory and i/o devices.
Microprocessors are typically used as CPUs of computers while microcontrollers are used in embedded devices.
Each microprocessor has a fixed set of instructions in the form of binary patterns called a machine language.
The binary instructions are given abbreviated names, called mnemonics , which form the assembly language for a given microprocessor.
Intel was developing a programmable calculator. The original design needed 12 different chips with hardwired logic functions. Ted Hoff suggested a general-purpose chip that could perform various logic functions which could be activated by providing patterns of 0s and 1s. Intel coined the term microprocessor and in 1971 released the first microprocessor as the Intel 4004.
Gordon E. Moore predicted that the number of transistors will double in integrated circuits manufactured in every 18 months. ( Moore’s law )
Evolution: 4004 4040 8008 8080 8085 8086 8088 80186 80188 80286 80386 80486 Pentium
Chapter 2
8086 Machine Organization
Overview
Intel 8086
- Designer: Stephen Paul Morse
- Released in 1979
- HMOS technology
- 40-pin DIP
- CPU clock rate = 5 MHz to 10 MHz (higher than Intel 8085)
- 16-bit ALU
- 16-bit data bus and 20-bit address bus
- Lower-order address bus and data bus multiplexed
- Better support for high-level languages than previous microprocessors
- 24 addressing modes
- Bit, byte, word, and block operations
- 8- and 16-bit signed and unsigned arithmetic in binary or decimal including multiply and divide
- Memory segmentation
- 6-byte instruction pipeline
- Hardware-level support for program debugging
Block diagram:
EU: Execution unit BIU: Bus interface unit
Pointer and index registers: 15 0 SP Stack pointer BP Base pointer SI Source index DI Destination index
Segment registers: 15 0 CS Code DS Data SS Stack ES Extra
Instruction pointer and flags: 15 0 IP FLAGS D O I T S Z A P C
IP is not directly accessible to the programmer.
Status flags:
- Carry flag (CF)
- Auxiliary carry flag (AF)
- Parity flag (PF) – set if there are even numbers of 1s in the result.
- Zero flag (ZF)
- Sign flag (SF)
- Overflow flag (OF) – indicates a signed result that is out of range.
Control flags:
- Direction flag (DF) – direction of string manipulation instructions.
- Interrupt-enable flag (IF) – enables / disables external interrupts.
- Trap flag (TF) – puts processor in a single-step mode for program debugging.
Instruction Operands and Operand-addressing Modes
Format 1: Single-operand instruction with the operand in a 16-bit register. (Register addressing mode) opcode reg
reg 16 - bit register 8 - bit register 000 AX AL 001 CX CL 010 DX DL 011 BX BL 100 SP AH 101 BP CH 110 SI DH 111 DI BH
Format 2: Single-operand instruction with the operand in an 8- or 16-bit register. (Register addressing mode) opcode w mod opcode reg 1 1 mode = 11
Width field (w) If w = 0: 8-bit operand. If w = 1: 16-bit operand.
Format 3: Single-operand instruction with the operand in memory. (Indirect addressing mode) ( variants) opcode w mod opcode m
mode = 00, 01, 10. Offset = base register + index register + displacement. m specifies the base register and index register. mod specifies how to calculate the 16-bit displacement.
m Base register Index register 000 BX SI 001 BX DI 010 BP SI 011 BP DI 100 - SI 101 - DI 110 BP - 111 BX - Not applicable if mod=11. Not applicable if mod=00 and m=110.
If BX is used, then operand is in current data segment. If BP is used, then operand is in current stack segment.
mod Displacement Additional bytes 00 00000000 00000000 0 01 00000000 next-byte 1 10 next-to-next-byte next-byte 2 Not applicable if mod=00 and m=110.
Address = segment register << 4 + offset.
Format 4: Use of segment overriding prefix. Operands can be fetched from all four current segments; not just the current data segment and current stack segment. The instruction should have a 1-byte prefix. seg 0 0 1 1 1 0
opcode s w mod opcode reg lower-order data higher-order data 1 1 1 mode = 11 higher-order data present only if s = 0 One byte is eliminated by using s field.
Format 12. Immediate-operand instruction with one operand in memory. (Immediate addressing mode) (2 variants) opcode s w mod opcode m lower-order data higher-order data 1 1 1 mode = 00, 01, 10 higher-order data present only if s = 0
Exercise> Analyze the following instructions. (a) 01000101 – Format 1, INC (b) 11111110 11000001 – Format 2, INC (c) 11111111 01000100 01011100 – Format 3, INC. Assume SI = 10100000 10000110 (d) 00100110 11111111 01000100 01011100 – Format 4, INC (e) 11111110 00000110 11110000 01011010 – Format 5, INC (f) 00000010 11101011 – Format 6, ADD (g) 10111111 00001111 11110000 – Format 8, MOV (h) 11000111 00000111 00001111 11110000 – Format 10, MOV (i) 10000011 00000111 00001111 – Format 12, ADD
Chapter 3
8086 Instruction Set
Overview
Several instructions have a general (long) form as well as a restricted (short) form. The short form
- uses fewer bytes
- less options for choosing operands
- used for frequently used cases Programmer need not worry, assembler will choose proper form.
Instructions
- data transfer instructions
- general-purpose transfers
- accumulator-specific transfers
- address-object transfers
- flag transfers
- arithmetic instructions
- addition
- subtraction
- multiplication
- division
- formatting
- logical instructions
- string instructions
- transfer of control instructions
- unconditional transfer
- conditional transfer
- interrupt instructions
- flag instructions
- synchronization instructions
- synchronization with subordinate processors
- resource sharing
Data Transfer Instructions
A segment register can be used as an operand. No sense of modifying a segment register; so no other instruction has a segment register as an operand.
General-purpose transfers
MOV
Accumulator-specific transfers
IN
Input to AL/AX. 1110010 w port Direct addressing mode. Can access only the first 256 ports.
Input to AL/AX. 1110110 w Indirect addressing mode. Use DX as port address. Can access only all 2^16 ports.
OUT
Output from AL/AX. 1110011 w port
Output from AL/AX. 1110111 w
XLAT (Translate) Transfer a byte from a table to AL. Base of table stored in BX and index in AL originally. Implied addressing mode.
Address-object transfers
LEA (Load effective address) Copy offset of m to reg. 10001101 mod reg r/m mod = 00, 01, 10 Used to pass the offset of a variable from one part of a program to another part. Used to implement call by reference.
LDS (Load pointer to DS) 11000101 mod reg r/m mod = 00, 01, 10 reg mem+1, mem DS mem+2, mem+ Used to set segment start address and offset. The combination of segment start address and offset is called a pointer.
LES (Load pointer to ES) 11000100 mod reg r/m mod = 00, 01, 10 reg mem+1, mem ES mem+2, mem+
Flag transfers
LAHF (Load AH with flags) Lower-order flags only.
SAHF (Store AH into flags)
PUSHF (Push flags) Push lower-order flags first then higher-order flags.
POPF (Pop flags)
Arithmetic Instructions
Add and subtract instructions set CF if the result, as interpreted as a unsigned number, is out of range. Add and subtract instructions set OF if the result, as interpreted as a signed number, is out of range.
Exercise> Add as signed and unsigned numbers. (a) 00000111 + 11111011 (b) 00001001 + 01111100
Addition
ADD
Add register/memory with register. 000000 d w mod reg r/m
Add immediate with register/memory. 100000 s w mod 000 r/m lower-order data higher-order data higher-order data present only if s = 0.
Add immediate with accumulator. 0000010 w lower-order data higher-order data
ADC (Add with carry)
Add with carry register/memory with register. 000100 d w mod reg r/m
Add with carry immediate with register/memory. 100000 s w mod 010 r/m lower-order data higher-order data higher-order data present only if s = 0.
Add with carry immediate with accumulator. 0001010 w lower-order data higher-order data
INC
Division
8 - bit 16 - bit Dividend AX DX AX Divisor Operand Operand Quotient AL AX Remainder AH DX
DIV
Unsigned divide. 1111011 w mod 110 r/m
IDIV
Signed divide. 1111011 w mod 111 r/m
Formatting
CBW (Convert byte to word) Extends sign bit of AL into all bit of AH.
CWD (Convert word to double word) Extends sign bit of AX into all bit of DX.
DAA (Decimal adjust for addition)
DAS (Decimal adjust for subtraction)
AAA (ASCII adjust for addition)
AAS (ASCII adjust for subtraction)
AAM (ASCII adjust for multiplication)
AAD (ASCII adjust for division)
Logical Instructions
Boolean
NOT
AND
OR
XOR
TEST
Same as AND but operands are not modified.
Shift and rotate
SHL (Shift logical left) CF Destination 0 Used for unsigned numbers.
SHR (Shift logical right) 0 Destination CF
SAL (Shift arithmetic left) CF Destination 0 Used for signed numbers.
SAR (Shift arithmetic right) Sign bit Destination CF
ROL (Rotate left)
ROR (Rotate right)
RCL (Rotate left through carry)
RCR (Rotate right through carry)
String Instructions
A string is a sequence of bytes or words in the memory. A string operation is one that is performed on each element of a string. Intel 8086 supports string instructions that decreases the time required for performing string operations. This is achieved by reducing the time taken to process each element and eliminating overhead and bookkeeping.
Elementary
MOVS (Move string elements) CX contains the number of bytes or words to be moved. DS and SI specify the source. ES and DI specify the destination. DS = ES (may be). Overlapped source and destination?
1111001 w
Direction flag (DF) If DF = 0: progress in forward direction. If DF = 1: progress in backward direction.
Transfer of Control Instructions
Unconditional transfer
Jump, call and return instructions may be either intra-segment or inter-segment. Inter-segment jump, call and return instructions changes the value of CS, transfer the control to an arbitrary segment which becomes the current code segment. An inter-segment call saves the CS and IP on the stack; while an inter-segment return removes two words from the stack and places them in CS and IP. Intra-segment call and return save and restore IP only.
JMP
Jump direct intra-segment. 11101001 diff-low diff-high
Jump direct intra-segment (short). 11101011 diff
Jump indirect intra-segment. 11111111 mod 100 r/m
Jump direct inter-segment. 11101010 offset-low offset-high seg-low seg-high
Jump indirect inter-segment. 11111111 mod 101 r/m
CALL
Call direct intra-segment. 11101000 diff-low diff-high
Call indirect intra-segment. 11111111 mod 010 r/m
Call direct inter-segment. 10011010 offset-low offset-high seg-low seg-high
Call indirect inter-segment. 11111111 mod 011 r/m
RET
Return intra-segment. 11000011
Return intra-segment, adding immediate to SP. 11000010 data-low data-high
Return inter-segment. 11001011
Return inter-segment, adding immediate to SP. 11001010 data-low data-high
Conditional transfer
No conditional call and return supported. Only short intra-segment jumps supported. J?? diff
JE/JZ
JNE/JNZ
JL/JNGE (SF xor OF) = 1 JNL/JGE (SF xor OF) = 0 JLE/JNG ((SF xor OF) or ZF)= 1 JNLE/JG ((SF xor OF) or ZF)= 0 JB/JNAE CF = 1 JNB/JAE CF = 0 JBE/JNA (CF or ZF) = 1 JNBE/JA (CF or ZF) = 0 JP/JPE JNP/JPO JO JNO JS JNS
Interrupt Instructions
2 pins: Non-maskable interrupt (NMI) and interrupt (INTR). NMI may be interrupted by a peripheral and is serviced irrespective of the status of IF. INTR may be interrupted by a peripheral or the processor itself. An interrupt type may be specified with INTR. A table contains the starting addresses of the interrupt service routines. The table starts at memory location 0, and has 256 entries. Each entry is of 4 bytes, and contains the CS and IP corresponding to the starting address of the interrupt service routine. Processor saves flags, CS and IP before starting an interrupt service routine. Interrupt types 0 to 31 are reserved, and are serviced irrespective of the status of IF. Interrupt type 0: division by zero. Interrupt type 1: single stepping. Interrupt type 2: NMI. Interrupt type 3: 1-byte INT instruction. Interrupt type 4: signed overflow. Interrupt types 5-31: future use. Processor generates an interrupt type 0 when it attempts to divide by zero. Signed overflow does not automatically generate an interrupt.
WAIT
Waits for subordinate processor to complete processing. When subordinate processor completes it send a signal to the TEST pin. WAIT should precede ESC.
Resource sharing
1-byte LOCK prefix to synchronize with other processors. Puts a high signal on the LOCK pin during the execution of the following instruction.
Chapter 5
8086 Assembly Language Programming
Token
Tokens
- Identifiers
- Reserved words
- Delimiters
- Constants
- Comments
Identifiers
- Names of variables, labels, subroutines and segments
- Sequence of letters, digits and underscore characters (_)
- May not start with a digit
- Up to 31 characters long
Reserved words
- Instruction mnemonics (MOV, ADD, SUB, etc.)
- Register names (AH, AL, AX, etc.)
- Directives (ASSUME, DB, DW, etc.)
- Miscellaneous (DUP, EQ, NE, etc.)
Delimiters
- / = < >? & $ ( ) [ ] ,. ‘ : ;
Constants
- Whole-number constants
- 0 to 65535
- Suffices: B (binary), Q (octal), H (hexadecimal)
- May not start with a letter, use a leading 0.
- String constants
- One or two characters enclosed by a pair of ‘.
- ASCII values of characters used.
Comments
- From ; to the end of line
Expression
Expressions
- Sequence of operands and operators that can be evaluated at the assemble time
- Permissible range of values: -65535 to +
- Value of an expression can be negative but a constant cannot be negative; - treated as operator
Operators
