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Input Device
Output CPU Device
Memory
3BCA5 Introduction to Microprocessor Unit -
A microprocessor is an integrated circuit which has the ability to mimic the processes executed by the processing unit. The integrated circuit accepts data as an input and process it according to instruction code to generate an information. With the use of input device, processing unit can get the input and after processing the input, processor will give the information to the user with the help of output device. The integrated circuit was also designed which has an ability to store the data, instruction code and information. The processing unit reads instruction code from this circuit and act accordingly. The system with central processing unit, input device, output device and memory can be visualized as shown in the figure 1.1. The processor as an integrated circuit in a very small size hence referred Microprocessor Data Data Information Information
Data Instruction Code Information
fig 1.1 Block diagram of a Computer
Simple Model of Microprocessor
fig 1.2 Simple model of Microprocessor
fig 1.2 is a simple seqential digital circuit which consists od 4 bit counter, 2 decoders, registers, switch control circuit, control unit arithmetic logic unit and bus.
Prof. Parimal Kumar K.R
1.1 Counter
It is a 4 bit counter, which starts counting from 0 and ends at 15 (0000 – 1111). The counter is driven by the clock signal and the output is given to Decoder A through 4 lines referred as address bus.
1.2 Decoder A
It is a 4 : 16 Decoder which activate its output depending on the status of inputs. The output of the decoder is used to select one of the registers within the register array.
1.3 Register Array
fig 1.3 Register Array wit tri-state switches
The above figure shows the register array consists of sixteen 3 bit registers. The output of all the registers are connected to a common bus through the Output Enable (OE) switch
The output of the Decoder A is used to active output enable signals of sixteen registers (R 0 - R 15 ). At a time only one output of decoder is activated according to the output signal, so data of only one register is available on the common bus.
AND : This control circuit generated control signals to perform AND operation in ALU. [ A ] Ʌ [ B ] = [ C ]
OR : This control circuit generated control signals to perform OR operation in ALU. [ A ] V [ B ] = [ C ]
LOAD A : This control circuit generates control signals which activate input enable signal for register A. It also indicates switch control circuit to change switch position to A.
LOAD B : This control circuit generates control signals which activate input enable signal for register B. It also indicates switch control circuit to change switch position to B.
1.7 ALU
ALU takes input from register A and register B and processes it according to the operation selected by the control unit. The processed result is stored in register C.
1.8 Switch Control Circuit
Switch control circuit is responsible for switch position. It gets the input from LOAD A, LOAD B control circuits. If any of the input s is activated, it changes switch position to A, otherwise it hold switch at position B.
Operations
The counter starts from zero. When counter output is zero, decoder A selects the first register R 0
from the register array and the data from the selected register R 0 is availabe on the common bus.
Initially switch is at position B , so the data moves to register I and then to Instruction decoder
(Decoder B). Decoder B decodes the instruction. According to data, control unit selects the
operation and ALU performs the operation.
The data selected from one of the register decides the type of the operation. The data which decides the
operation is referred as “operation code” or “OpCode”. As mentioned in table 1.1. each operation has its own operational code.
In operation MOV A,C and MOV B,C the data is transferred from register C to register A or B respectively. In operation ADD, SUB, AND and OR the processing data is taken from register A and register B. In operation LOAD A and LOAD B data from common bus is directly loaded into register A and register B respectively. For last 2 operations switch must be in position A
After each operation is couter is incremented by one, so that the decoder selects the next register. Again the data from selected register is available on the common bus and the process is repeated.
Different phases in the execution process
Different phases in the execution process are
1. Fetch microprocessor places the contents of the program counter on the address bus and gets the instruction code, opcode from the address memory location. The microprocessor then saves opcode in the instruction register. 2. Decode The instruction from the instruction register is decoded with the help of instruction decoder to generate appropriate control signals to execute the instuction. 3. Execute Microprocessor generates appropriate control signals and executes the instruction.
Example to Add 2 numbers.
Problem : Add 2 numbers ( 5 + 2)
Procedure : 1. Load first number in register A
- Load second number in register B
- Add 2 numbers in accumulator
Steps : 1. LOAD A
- 5
- LOAD B
- 2
- ADD Equivalent Code in register:
- 110
- 101
- 111
- 010
- 010
First step is to load the number in register A. So, the opcode to do this should be stored in register R 0 and the value for register A is stored in register array R 1. Similarly for second value. The opcode to load register B is in register R 2 and second value is in register R 3. The opcode to add is stored in register R 4.
STEP 1 : Output of COUNTER is 0 (0000) In the beginning the counter output is 0 (0000). This output value is given as input to 4 : 16 Decoder (A) which selects register R 0 from register array. The value in register is 110 which is available in common bus. The Instruction decoder (3 : 8 Decoder B) will use this data to select the operation. Data is 110. So, it selects LOAD A operation. LOAD A operation will enable input for register A and change the switch position from B to A (fig 1.4).
STEP 2 : Output of COUNTER is 1 (0001) Counter output is 1 (0001). This output value is given as input to 4 : 16 Decoder (A) which selects register R (^1) from register array. Now the value 101 is availabe on the common bus. This value is moved directly to register A because switch is positioned at A and input to register A is enabled. After the data transfer switch position is changed from position A to position B.
STEP 3 : Output of COUNTER is 2 (0010) Counter output is 2 (0010). This output value is given as input to 4 : 16 Decoder (A) which selects register R (^2) from register array. The value in register is 111 which is available in common bus. The Instruction decoder (3 : 8 Decoder B) will use this data to select the operation. Data is 111. So, it selects LOAD B operation. LOAD B operation will enable input for register B and change the switch position from B to A.
STEP 4 : Output of COUNTER is 3(0011) Counter output is 3 (0011). This output value is given as input to 4 : 16 Decoder (A) which selects register R (^3) from register array. Now the value 010 is availabe on the common bus. This value is moved directly to register B because switch is positioned at A and input to register B is enabled. After the data transfer switch position is changed from position A to position B.
STEP 5 : Output of COUNTER is 4(0100) Counter output is 4 (0100). This output value is given as input to 4 : 16 Decoder (A) which selects register R (^4) from register array. The value in register is 111 which is available in common bus. The Instruction decoder (3 : 8 Decoder B) will use this data to select the operation. Value is 010. So, it selects ADD operation which
The 8085 Microprocesor Microprocessor 8085 is an 8 bit NMOS single chip with approx 6200 transistors on 166 X 222 mil chip contained in a 40 pin dual in line package.
Features of 8085 microprocessor are
- It is an 8 bit microprocessor. It can accept, process and provide data simultaneously.
- It has 16 bit address bus. The lower 8bit address bus (A0 to A7) and 8 bit data bus (D0 to D7) are multiplexed and used as address lines. An address latch is used to separate address and data lines.
- As it is having 16 address lines, it can access (216) 64K memory locations.
- It requires a signal +5V power supply and operates at 3.2 MHZ single phase clock with maximum clock frequency 6 MHz and minimum clock frequency 500 kHz.
- It has on chip clock generator. This internal clock gererator requires tuned circuit. The internal clock generator divides oscillator frequency by 2 and geneates clock signal, which can be used to synchronize external devices.
- It supports 74 instruction sets.
- The ALU performs 8bit addition with and without carry, 16 bit addition, 2 digit BCD addition, 8 bit subtraction with and without borrow and 8 bit logical operations like OR, AND, EX-OR, complement & bit shift operations.
- It provides 8bit accumulator, flag register, six 8-bit general purpose register arranged in pairs: BC, DE, HL, 2 sixteen bit special purpose registers and instruction register.
- It has an ability to share system bus with Direct Memory Access controller. This feature allows to transfer largr amount of data from I/O device to memory or vice versa.
- It provides 5 hardware interrupts : TRAP, RST 5.5, RST 6.5, RST 7.5, INTR.
- It has serial I/O controls like SID and SOD for serial communications.
- It provides signals to control the bus cycles like IO/MP, RD and WR
- The external hardware can detect which machine cycle is executed by the microprocessor using status signals like IO/M, S 0 and S 1
Architecture of 8085 Microprocessor
fig 2.1 Architecture of 8085 microprocessor
It consists of various functional blocks. They are
1. Registers
The registers can be classified as a. General purpose registers
It has 6 general purpose registers B,C,D,E,H,L which can be used as a 8 bit registers or in pairs as 16 bit registers BC, DE and HL. When used in pairs the higher order byte resides in the first register and the lower order byte in the second register. Example Higher order in B and lower order byte in C.
The special HL pair functions as a pointer to memory location. These registers is also called scratch pad registers. Bus access is not required to store and load onto these registers. Thse can be used to store intermediate results.
b. Temporary registers i. Temporary data registers These registers are nor accesible. It is internally used for execution of arithemtic and logical operations. The ALU has 2 inputs. One input is supplied by the accumulator and another from the data registers.
ii. W and Z registers These are 8bit registers which cannot be accessible.
The CALL instruction is used to transfer the program counter to a sub program. This instruction pushes the content of program counter to the stack and loads the first instruction address of the subroutine in to the program counter. The given address is temporarily stored in W nad Z register and placed on the bus.
During XCHG instruction the data in H & L is transferred to D & E register respectively. At the time of exchange W and Z registers are used to temporarily store the data.
c. Special purpose registers. i. Register A (Accumulator) It is a tri state 8 bit register. It is extensively used in arirthmetic, logic, store load and I/O operations. The result of arithmetic and logical operations are stored in the register A. It is also called as accumulator.
ii. Flag register In a 8 bit register, 5 bits carry significant information in the form of flags. They are D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 S Z X AC X P X CY
Sign flag (S) : The D7 bit is set (1) after the execution of arithmetic or logical operations if the resultant is a negetive number. For positive numbers the value will in D7 is 0. Zero flag (Z) : In the ALU, after an operation if the result is zero the D6 bit is set (1). The flag also sets to zero if a certain register content becomes zero after an increment or decrement operation in that particulat register.
Shifter : It performs logical operations like rotate left, rotate right, etc.The result of operation is again stored into accumulator. Status Register : Also known as flag register. It contains a no. of flags either to indicate conditions arising after last ALU operation or to control certain operations.
3. Instruction Decoder
The instruction decoder decodes the opcode received from the instruction register. Depending upon the nature of the instruction it gives timing and control signals which controls the register , the data buffer, ALU and the external peripheral signals. It also gives the information about which machine cycle is currently executing in the encoded form on the S 0 , S 1 and IO/M lines.
4. Address Buffer
It is an 8 bit unidirectional buffer. It is used to drive external high order address bus. (A 15 – A 8 )
5. Address / Data Buffer
It is an 8 bit bidirectional buffer. It is used to drive multiplexed address/data bus i.e, low order
address bus (A 7 – A 0 ) and data bus (D 7 – D 0 ).
6. Increment or decrement address latch
It is a 16 bit register used to increment or decrement the content of program counter or stack pointer as a part of instruction execution.
7. Interrupt control
Consider a microprocessor is executing the main program. Now whenever the interrupt signal is enabled or requested the microprocessor temporarily stops the execution of main program and transfers control to specific special routine known as "Interrupt Service Routine"(ISR). After the completion of request, the control goes back to the main program.
There are 5 interrupt signals present in 8085.They are: I. INTR II. RST 7. III. RST 6. IV. RST 5. V. TRAP
TRAP is a NON-MASKABLE interrupt control and other three are maskable interrupts. A non- maskable interrupt is an interrupt which is given the highest priority in the order of interrupts. Non- maskable interrupt cannot be disabled by programmer at any point of time. Whereas, the maskable interrupts can be disabled and enabled using EI and DI instructions. Among the maskable interrupts RST 7. is given the highest priority above RST 6.5 and least priority is given to INTR.
8. Serial IO control
In serial communication one bit is transferred at a time over the single line. In this processor, serial IO control provides two lines SID and SOD for serial communication. The serial output data line (SID) is used to send the data and serial input data line (SOD) is used to receive the data serially.
9. Timing and control circuitry.
The operation in microprocessor are synchronized using the clock signals. Along with the control of fetching and decoding operations and generating appropriate signals for instruction execution, control circuitry also generates signals required to interface external devices with the processor.
Pin definition of 8085
fig 3.1 8085 Pin Diagram fig 3.2 Functional pin diagram
The signals of 8085 can be classified into 7 groups according to their functions.
- Power supply and frequency signals
- Data bus and address bus.
- Control Bus.
- Interrupt signals.
- Serial I/O signals.
- DMA signals.
- Reset signals
2. RST 7.5,RST 6.5 and RST 5.5: These are active high, edge (RST 7.5) or level (RST 6.5 and RST 5.5) triggered maskable interrupts.The priorities of these are TRAP, RST 7.5, RST 6.5, and RST 5.5. When RST 7.5, RST 6.5 and RST 5.5 are active, the program counter jumps automatically at address 003C, 0034, 002C respectively. 3. INTR and INTA: INTR is an active high, level triggered general purpose interrupt. When INTR is active microprocessor generates an interrupt acknowledge signal INTA. If INTR is active, the Program Counter (PC) will be restricted from incrementing and an INTA will be issued. During This cycle a RESTART or CALL instruction can be inserted to jump to the interrupt Service routine. The INTR is enabled and disabled by software. It is disabled by Reset And immediately after an interrupt is accepted.
5. Serial I/O Signals
a. SID : This is an active high Serial input data line the data on this line is loaded into accumulator bit 7 whenever a RIM instruction is executed. This signal is used to accept serial data bit by bit from the external device.
b. SOD : This is an active high Serial output data line. The output SOD is set or reset as specified by the SIM instruction. This signal enables the transmission of data serially bit by bit to the external device.
6. DMA Signal
a. HOLD : HOLD indicates that another Master is requesting the use of the Address and Data Buses. The CPU, upon receiving the Hold request, will withdraw the use of buses as soon as the completion of the current machine cycle. Internal processing can continue. The processor can regain the buses only after the Hold is removed. When the Hold is Acknowledged, the Address, Data, RD, WR, and IO/M lines are tristated.
b. HLDA : HOLD ACKNOWLEDGE indicates that the CPU has received the Hold request and that it will withdraw the buses in the next clock cycle. HLDA goes low after the Hold Request is removed. The CPU takes the buses one half clock cycles after HLDA goes Low.
7. RESET Signals
a. RESET IN : Reset sets the Program Counter to zero and resets the Interrupt Enable and HLDA Flip- flops and makes address, data and control lines tristated. The CPU is held in the reset condition as long as Reset is applied. After reset status of internal register and flag are unpredictable. After reset microprocessor starts executing the instruction from 0000H onwards.
b. RESET OUT : This is an active high output signal used to indicate CPU is being reset and can be used as a system RESET. The signal is synchronized to the processor clock. This signal is also used to reset the peripherals once the microprocessor is reset. It is an acknowledgement signal to RESET IN.
Exercise Questions
1. Explain with diagram the architecture of microprocessor 8085.
2. Explain with diagram the pin diagram of microprocessor 8085. Explain the purpose of each pin in
8085 microprocessor.
3. Why AD0 to AD7 lines are multiplexed.
4. What are the functions of an accumulator.
5. How are interrupts classified in 8085.
