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Chapter 6: Memory

• Chapter 6: Memory – 1

CS140 Computer Organization

Chapter 6 Objectives

• Master the concepts of hierarchical memory

organization.

• Understand how each level of memory contributes to

system performance, and how the performance is

measured.

• Master the concepts behind cache memory, virtual

memory, memory segmentation, paging and address

translation.

• Chapter 6: Memory – 2

6.3 The Memory Hierarchy

• Chapter 6: Memory – 4
• Faster memory is more expensive than slower memory.
• For the best performance at the lowest cost, memory is organized in a

hierarchical fashion.

• Small, fast storage elements are kept in the CPU, larger, slower main memory

is accessed through the data bus.

• Larger, (almost) permanent storage in the form of disk and tape drives is still

further from the CPU.

Control

Datapath

Secondary Storage (Disk)

Processor

Registers

Main Memory (DRAM)

Second Level Cache (SRAM)

On-Chip Cache

Tertiary Storage Third (Tape) Level Cache (SRAM)

6.3 The Memory Hierarchy

Let’s look at numbers for an Intel Pentium 4, 3.2 GHz Server.

• Chapter 6: Memory – 5

Component Access Speed

(Time for data to be returned)

Size of Component

Registers 1 cycle = 0.3 nanoseconds

8 registers

L1 Cache 3 cycles = 1 nanoseconds

Separate Data and Instruction Caches: 16 Kbytes each

L2 Cache 20 cycles = 7 nanoseconds

256 Kbytes, 8-way set associative

L3 Cache 40 cycles = 13 nanoseconds

4096 Kbytes, 8-way set associative

Memory 300 cycles = 100 nanoseconds

16 Gigabytes

Disk 30,000,000 cycles = 10 milliseconds

400 Gigabytes

6.3 The Memory Hierarchy

Why Does It Work? Locality!

• Temporal Locality (Locality in Time):

Keep most recently accessed data items closer to the processor

• Spatial Locality (Locality in Space):

Move blocks consisting of contiguous words to the upper levels

• Chapter 6: Memory – 7

Lower Level Upper Level Memory Memory

To Processor

From Processor

Blk X Blk Y

(^0) Memory Address 2 n (^) – 1

Probability of reference

6.3 The Memory Hierarchy

• An entire blocks of data is copied after a hit because the principle of

locality tells us that once a byte is accessed, it is likely that a nearby data

element will be needed soon.

• There are three forms of locality:
  • Temporal locality - Recently-accessed data elements tend to be

accessed again.

• Spatial locality - Accesses tend to cluster.
• Sequential locality - Instructions tend to be accessed sequentially.
• Cache Line -- The number of bytes brought in with this block
• Chapter 6: Memory – 8

6.3 The Memory Hierarchy

• Chapter 6: Memory – 10
• Hit: data appears in some block in the upper level (example: Block X)
• Hit Rate: the fraction of memory access found in the upper level
• Hit Time: Time to access the upper level which consists of

RAM access time + Time to determine hit/miss

• Miss: data needs to be retrieve from a block in the lower level (Block Y)
  • Miss Rate = 1 - (Hit Rate)
  • Miss Penalty(Time): Time to replace a block in the upper level +

Time to deliver the block the processor

• Hit Time << Miss Penalty

“Lower Level” “Upper Level” Memory Memory

To Processor

From Processor

Blk X Blk Y

6.3 The Memory Hierarchy

• HISTORY
• “Out-of-Core”, “In-Core,” “Core Dump”?
• “Core memory”?
• Non-volatile, magnetic
• Lost to 4 Kbit DRAM (today using 2 Gigabit DRAM)
• Access time 750 ns, cycle time 1500-3000 ns  what would be the

processor speed for a machine using this memory?

• Chapter 6: Memory – 11

SDRAM; Random Access Memory

• Short for Synchronous DRAM, a type of DRAM that can run at much higher clock

speeds than conventional memory. SDRAM actually synchronizes itself with the

CPU's bus and is capable of running at 133 MHz,

DDR (Double Data Rate) is a technology used in some SDRAM memories to

increase the speed at which data can be written/retrieved from the memory.

DDR increase the transfer rate by sending/receiving memory data twice per clock

cycle. This give a theoretical multiplication of transfer speed by two.

DDR2-SDRAM maintains the same core functions, transferring 64 bits of data twice every clock cycle for an effective transfer rate twice that of the front-side bus (FSB) of a computer system, and an effective bandwidth equal to its speed x 8.

• Chapter 6: Memory – 13

6.3 The Memory Hierarchy

Random Access Memory

1 USB connector 2 USB mass storage controller device 3 Test points 4 Flash memory chip 5 Crystal oscillator 6 LED 7 Write-protect switch 8 Space for second flash memory chip

• Chapter 6: Memory – 14

6.3 The Memory Hierarchy

Flash Memory

A type of EEPROM.

Non-volatile – doesn’t require power to hold data.

Data is written in blocks - not byte accessible. Great for disk-like devices requiring 4096 bytes to be read/written; not good for Random Access Memory.

Limited to 1,000,000 cycles – and blocks can go bad.

The controller can do bad block remapping and error checking.

The controller can do wear leveling – moving blocks around so that no one area on the chip has excessive wear.

6.4 Cache Memory

Motivation:

When I run a tool that looks at Memory hierarchy on a

machine, here’s what I get:

• Chapter 6: Memory – 16

So what do all these

words mean?

6.4 Cache Memory

• The purpose of cache memory is to speed up accesses by

storing recently used data closer to the CPU, instead of

storing it in main memory.

• Although cache is much smaller than main memory, its

access time is a fraction of that of main memory.

• Unlike main memory, which is accessed by address, cache

is typically accessed by content; hence, it is often called

content addressable memory.

• Because of this, a single large cache memory isn’t always

desirable-- it takes longer to search.

• Chapter 6: Memory – 17

6.4 Cache Memory

• The simplest cache mapping scheme is direct mapped

cache.

• In a direct mapped cache consisting of N blocks of cache,

block X of main memory maps to cache block Y = X mod N.

• Thus, if we have 10 blocks of cache, block 7 of cache may

hold blocks 7, 17, 27, 37,... of main memory.

• Once a block of memory is copied into its slot in cache, a

valid bit is set for the cache block to let the system know

that the block contains valid data.

• Chapter 6: Memory – 19

What could happen if there were no valid bit?

6.4 Cache Memory

• The diagram below is a schematic of what cache looks like.
• Block 0 contains multiple words from main memory,

identified with the tag 00000000. Block 1 contains words

identified with the tag 11110101.

• The other two blocks are not valid.
  • Chapter 6: Memory – 20