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4 problems, 4 pages Exam Three Solutions 29 November 2006
Problem 1 (2 parts, 24 points) Counters
Part A (12 points) Design a toggle cell using transparent latches and basic gates. Use an icon for the latch. Your toggle cell should have an active high toggle enable input TE , and an active low clear input -Clear , clock inputs Φ 1 and Φ 2 , and an output Out. The - Clear signal has precedence over TE. Label all signals.
In Out
En
Latch
In Out
En
Latch
TE Out
CLR
Part B (12 points) Now combine these toggle cells to build a divide by seven counter. Your counter should have an external clear, external count enable, and three count outputs O 2 , O 1 , O 0. Use any basic gates (AND, OR, NAND, NOR, & NOT) you require. Assume clock inputs to the toggle cells are already connected. Your design should support multi-digit systems.
O^0
O 1
O^2
Ext Clr
Ext CE TE
Out Clr
TE Out Clr
TE Out Clr
4 problems, 4 pages Exam Three Solutions 29 November 2006
Problem 2 (2 parts, 18 points) Datapath Elements
Part A (9 points) Consider the following input and output values for a shift operation. Determine the shift type and amount required to achieve the listed transformation. There are no overflows. Input Value Output Value Shift Type Shift Amount (signed decimal value) (^87654321 54321876) rotate -12 or +20 bits
87654321 FFFF8765 (^) arithmetic +16 bits
(^87654321 76543210) logical -4 bits
Part B (9 points) Consider the following input and output values for a logical operation. Determine the logical function and function code (in hexadecimal) required for the operation. X Input Y Input Output Logical Function Function Code 12345678 0F0F0F0F 1F3F5F7F (^) OR E
12345678 0F0F0F0F (^02040608) AND 8
12345678 0F0F0F0F 1D3B5977 (^) XOR 6
Problem 3 (3 parts, 31 points) Memory Systems
Part A (10 points) Consider a 1 Gbit DRAM chip organized as 16 million addresses of 64 bit words. Assume both the DRAM cell and the DRAM chip is square. The column number and offset concatenate to form the memory address. Using the organization approach discussed in class, answer the following questions about the chip. Express all answers in decimal.
number of columns (^) square root (1G = 2^30 ) = 2 15 = 32K
column decoder required ( n to m ) (^) 15 to 32K type of mux required ( n to m ) (^) 32K/64 = 512 to 1 mux
number of muxes required (^) 64 muxes number of address lines in column number (^15) number of address lines in column offset (^9)
Part B (10 points) Consider a 2 Gbyte memory system with 128 million addresses of 16 byte words using 1 Gbit DRAM chips organized as 16 million addresses by 64 bit words.
word address lines for memory system (^27)
chips needed in one bank (^) 16 bytes/word / 8 bytes/chip = 2 chips banks for memory system (^) 128M / 16M = 8 banks/sys
memory decoder required ( n to m ) (^) 3 to 8 DRAM chips required (^) 2 chips/bank x 8 banks = 16 chips
4 problems, 4 pages Exam Three Solutions 29 November 2006
Problem 4 (3 parts, 27 points) Microcode
Using the supplied datapath, write microcode fragments to accomplish the following procedures. Express all values in hexadecimal notation. Use ‘X’ when a value is don’t cared. For maximum credit, complete the description field. Recall that ⊕ means XOR. Use only registers 1, 2, and 3.
Part A (15 points) 8
1
R R R
R.
# X Y Z rwe im en
im va au en
-a /s
lu en
lf su en
st description
(^1 2 3 2 1 0) X 0 X 1 6 0 X R2 <- R2 xor R
2 1 X 1 1 1 FFFE 0 X 0 X 1 1 R1 <- R1 * 4
3 1 2 1 1 0 X 1 0 0 X 0 X R1 <- R2 + R
4 1 X 1 1 1 0005 1 1 0 X 0 X R1 <- R1 - 5
(^5 1) X 1 1 1 0003 0 X 0 X 1 1 R1 <- R1 / 8
Part B (6 points) Assume R 1 contains three packed unsigned integer bytes (A, B, and C). Assume A is the least significant byte, then B, then C. Write a microcode fragment that unpacks B, placing it in the lowest eight bits of R 1. All other bits should be zero. # X Y Z rwe im en
im va au en
-a /s
lu en
lf su en
st description
(^1 1) X 1 1 1 0008 0 X 0 X 1 0 R1 <- R1 >> 8
(^2 1) X 1 1 1 00FF 0 X 1 8 0 X R1 <- R1 & FF
Part C (6 points) Write a microcode sequence that averages the initial values of R 1 and R 2. The result should be placed in R 1. # X Y Z rwe im en
im va au en
-a /s
lu en
lf su en
st description
(^1 1 2 1 1 0) X 1 0 0 X 0 X R1 <- R1 + R
2 1 X 1 1 1 0001 0 X 0 X 1 1 R1 <- R1 / 2
