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LM
SNAS548D – FEBRUARY 2000 – REVISED JANUARY 2015
LM555 Timer
1 Features 3 Description
1 • Direct Replacement for SE555/NE555 The LM555 is a highly stable device for generating
accurate time delays or oscillation. Additional
- Timing from Microseconds through Hours
terminals are provided for triggering or resetting if
- Operates in Both Astable and Monostable Modes (^) desired. In the time delay mode of operation, the time
- Adjustable Duty Cycle is precisely controlled by one external resistor and
- Output Can Source or Sink 200 mA capacitor. For a stable operation as an oscillator, the
free running frequency and duty cycle are accurately
- Output and Supply TTL Compatible (^) controlled with two external resistors and one
- Temperature Stability Better than 0.005% per °C capacitor. The circuit may be triggered and reset on
- Normally On and Normally Off Output falling waveforms, and the output circuit can source
or sink up to 200 mA or drive TTL circuits.
- Available in 8-pin VSSOP Package
Device Information(1)
2 Applications
PART NUMBER PACKAGE BODY SIZE (NOM)
- Precision Timing (^) SOIC (8) 4.90 mm × 3.91 mm
- Pulse Generation (^) LM555 PDIP (8) 9.81 mm × 6.35 mm
- Sequential Timing VSSOP (8)^ 3.00 mm × 3.00 mm
- Time Delay Generation (^) (1) For all available packages, see the orderable addendum at
- Pulse Width Modulation the end of the datasheet.
- Pulse Position Modulation
- Linear Ramp Generator
Schematic Diagram
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.
SNAS548D – FEBRUARY 2000 – REVISED JANUARY 2015 www.ti.com
Table of Contents
1 Features .................................................................. 1^ 7.3^ Feature Description................................................... 8
2 Applications ........................................................... 1^ 7.4^ Device Functional Modes.......................................... 9
3 Description ............................................................. 1^8 Application and Implementation^ ........................ 12
4 Revision History ..................................................... 2 8.1^ Application Information............................................ 12
5 Pin Configuration and Functions ......................... 3 8.2^ Typical Application ................................................. 12
6 Specifications ......................................................... 4^9 Power Supply Recommendations ...................... 15
6.1 Absolute Maximum Ratings ...................................... 4^10 Layout ................................................................... 15
6.2 ESD Ratings.............................................................. 4 10.1^ Layout Guidelines ................................................. 15 6.3 Recommended Operating Conditions....................... 4 10.2^ Layout Example .................................................... 15
6.4 Thermal Information ................................................. 4^11 Device and Documentation Support^ ................. 16
6.5 Electrical Characteristics .......................................... 5 11.1^ Trademarks ........................................................... 16 6.6 Typical Characteristics .............................................. 6 11.2^ Electrostatic Discharge Caution............................ 16
7 Detailed Description .............................................. 8 11.3^ Glossary ................................................................ 16
7.1 Overview ................................................................... 8^12 Mechanical, Packaging, and Orderable
7.2 Functional Block Diagram ......................................... 8 Information^ ........................................................... 16
4 Revision History
Changes from Revision C (March 2013) to Revision D Page
- Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes , Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1
Changes from Revision B (March 2013) to Revision C Page
- Changed layout of National Data Sheet to TI format ........................................................................................................... 13
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1) (2)
MIN MAX UNIT
LM555CM, LM555CN(4)^1180 mW Power Dissipation(3) LM555CMM 613 mW PDIP Package Soldering (10 Seconds) 260 °C Soldering (^) Vapor Phase (60 Seconds) 215 °C Information Small Outline Packages (SOIC and VSSOP) (^) Infrared (15 Seconds) 220 °C
Storage temperature, Tstg –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) If Military/Aerospace specified devices are required, please contact the TI Sales Office/Distributors for availability and specifications. (3) For operating at elevated temperatures the device must be derated above 25°C based on a 150°C maximum junction temperature and a thermal resistance of 106°C/W (PDIP), 170°C/W (S0IC-8), and 204°C/W (VSSOP) junction to ambient. (4) Refer to RETS555X drawing of military LM555H and LM555J versions for specifications.
6.2 ESD Ratings
VALUE UNIT V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)^ ±500(2)^ V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) The ESD information listed is for the SOIC package.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
Supply Voltage 18 V Temperature, TA 0 70 °C
Operating junction temperature, TJ 70 °C
6.4 Thermal Information
LM
THERMAL METRIC(1)^ PDIP SOIC VSSOP UNIT 8 PINS RθJA Junction-to-ambient thermal resistance 106 170 204 °C/W
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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6.5 Electrical Characteristics
(TA = 25°C, VCC = 5 V to 15 V, unless otherwise specified)(1) (2)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Supply Voltage 4.5 16 V Supply Current VCC = 5 V, RL = ∞ 3 6 VCC = 15 V, RL = ∞ 10 15 mA (Low State) (3)
Timing Error, Monostable Initial Accuracy 1 % Drift with Temperature RA = 1 k to 100 kΩ, 50 ppm/°C C = 0.1 μF, (4) Accuracy over Temperature 1.5 %
Drift with Supply 0.1 % V Timing Error, Astable Initial Accuracy 2. Drift with Temperature RA, RB =1 k to 100 kΩ, 150 ppm/°C C = 0.1 μF, (4)
Accuracy over Temperature 3.0% Drift with Supply 0.30 % /V Threshold Voltage 0.667 x VCC Trigger Voltage VCC = 15 V 5 V VCC = 5 V 1.67 V
Trigger Current 0.5 0.9 μA Reset Voltage 0.4 0.5 1 V Reset Current 0.1 0.4 mA Threshold Current (5)^ 0.1 0.25 μA Control Voltage Level VCC = 15 V 9 10 11 V VCC = 5 V 2.6 3.33 4 Pin 7 Leakage Output High 1 100 nA Pin 7 Sat (6) Output Low VCC = 15 V, I 7 = 15 mA 180 mV Output Low VCC = 4.5 V, I 7 = 4.5 mA 80 200 mV
Output Voltage Drop (Low) VCC = 15 V ISINK = 10 mA 0.1 0.25 V ISINK = 50 mA 0.4 0.75 V ISINK = 100 mA 2 2.5 V ISINK = 200 mA 2.5 V
VCC = 5 V ISINK = 8 mA V ISINK = 5 mA 0.25 0.35 V
(1) All voltages are measured with respect to the ground pin, unless otherwise specified. (2) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Recommended Operating Conditions indicate conditions for which the device is functional, but do not ensure specific performance limits. Electrical Characteristics state DC and AC electrical specifications under particular test conditions which ensures specific performance limits. This assumes that the device is within the Recommended Operating Conditions. Specifications are not ensured for parameters where no limit is given, however, the typical value is a good indication of device performance. (3) Supply current when output high typically 1 mA less at VCC = 5 V. (4) Tested at VCC = 5 V and VCC = 15 V. (5) This will determine the maximum value of RA + RB for 15 V operation. The maximum total (RA + RB) is 20 MΩ. (6) No protection against excessive pin 7 current is necessary providing the package dissipation rating will not be exceeded.
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Typical Characteristics (continued)
Figure 5. Low Output Voltage vs. Output Sink Current^ Figure 6. Low Output Voltage vs. Output Sink Current
Figure 7. Output Propagation Delay vs. Voltage Level of Figure 8. Output Propagation Delay vs. Voltage Level of Trigger Pulse Trigger Pulse
Figure 9. Discharge Transistor (Pin 7) Voltage vs. Sink Figure 10. Discharge Transistor (Pin 7) Voltage vs. Sink Current Current
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COMPARATOR
TRIGGER FLIP FLOP (^) COMPARATOR
RESET
+Vcc
DISCHARGE
THRESHOLD
Vref (int)
OUTPUT
STAGE
CONTROL VOLTAGE
OUTPUT
SNAS548D – FEBRUARY 2000 – REVISED JANUARY 2015 www.ti.com
7 Detailed Description
7.1 Overview
The LM555 is a highly stable device for generating accurate time delays or oscillation. Additional terminals are
provided for triggering or resetting if desired. In the time delay mode of operation, the time is precisely controlled
by one external resistor and capacitor. For astable operation as an oscillator, the free running frequency and duty
cycle are accurately controlled with two external resistors and one capacitor. The circuit may be triggered and
reset on falling waveforms, and the output circuit can source or sink up to 200mA or driver TTL circuits. The
LM555 are available in 8-pin PDIP, SOIC, and VSSOP packages and is a direct replacement for SE555/NE555.
7.2 Functional Block Diagram
7.3 Feature Description
7.3.1 Direct Replacement for SE555/NE
The LM555 timer is a direct replacement for SE555 and NE555. It is pin-to-pin compatible so that no schematic
or layout changes are necessary. The LM555 come in an 8-pin PDIP, SOIC, and VSSOP package.
7.3.2 Timing From Microseconds Through Hours
The LM555 has the ability to have timing parameters from the microseconds range to hours. The time delay of
the system can be determined by the time constant of the R and C value used for either the monostable or
astable configuration. A nomograph is available for easy determination of R and C values for various time delays.
7.3.3 Operates in Both Astable and Monostable Mode
The LM555 can operate in both astable and monostable mode depending on the application requirements.
- Monostable mode: The LM555 timer acts as a “one-shot” pulse generator. The pulse beings when the LM
timer receives a signal at the trigger input that falls below a 1/3 of the voltage supply. The width of the output
pulse is determined by the time constant of an RC network. The output pulse ends when the voltage on the
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Device Functional Modes (continued)
Figure 13 is a nomograph for easy determination of R, C values for various time delays.
Figure 13. Time Delay
7.4.2 Astable Operation
If the circuit is connected as shown in Figure 14 (pins 2 and 6 connected) it will trigger itself and free run as a
multivibrator. The external capacitor charges through RA + RB and discharges through RB. Thus the duty cycle
may be precisely set by the ratio of these two resistors.
Figure 14. Astable
In this mode of operation, the capacitor charges and discharges between 1/3 VCC and 2/3 VCC. As in the
triggered mode, the charge and discharge times, and therefore the frequency are independent of the supply
voltage.
Figure 15 shows the waveforms generated in this mode of operation.
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Device Functional Modes (continued)
VCC = 5 V Top Trace: Output 5V/Div. TIME = 20μs/DIV. Bottom Trace: Capacitor Voltage 1V/Div. RA = 3.9 kΩ RB = 3 kΩ C = 0.01 μF
Figure 15. Astable Waveforms
The charge time (output high) is given by:
t 1 = 0.693 (RA + RB) C (1)
And the discharge time (output low) by:
t 2 = 0.693 (RB) C (2)
Thus the total period is:
T = t 1 + t 2 = 0.693 (RA +2RB) C (3)
The frequency of oscillation is:
Figure 16 may be used for quick determination of these RC values.
The duty cycle is:
Figure 16. Free Running Frequency
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Typical Application (continued)
VCC = 5 V Top Trace: Input 4 V/Div. TIME = 20 μs/DIV. Middle Trace: Output 2V/Div. RA = 9.1 kΩ Bottom Trace: Capa citor 2V/Div. C = 0.01 μF
Figure 18. Frequency Divider
8.2.2.2 Additional Information
Lower comparator storage time can be as long as 10 μs when pin 2 is driven fully to ground for triggering. This
limits the monostable pulse width to 10 μs minimum.
Delay time reset to output is 0.47 μs typical. Minimum reset pulse width must be 0.3 μs, typical.
Pin 7 current switches within 30 ns of the output (pin 3) voltage.
8.2.3 Application Curves
The data shown below was collected with the circuit used in the typical applications section. The LM555 was
configured in the monostable mode with a time delay of 5.17 s. The waveforms correspond to:
- Top Waveform (Yellow) – Capacitor voltage
- Middle Waveform (Green) – Trigger
- Bottom Waveform (Purple) – Output
As the trigger pin pulses low, the capacitor voltage starts charging and the output goes high. The output goes low
as soon as the capacitor voltage reaches 2/3 of the supply voltage, which is the time delay set by the R and C
value. For this example, the time delay is 5.17 s.
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Typical Application (continued)
Figure 19. Trigger, Capacitor Voltage, and Output Waveforms in Monostable Mode
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11 Device and Documentation Support
11.1 Trademarks
All trademarks are the property of their respective owners.
11.2 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
11.3 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com (^) 21-Oct-
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1)
Package Type Package Drawing
Pins Package Qty
Eco Plan (2)
Lead/Ball Finish (6)
MSL Peak Temp (3)
Op Temp (°C) Device Marking (4/5)
Samples
LM555CM NRND SOIC D 8 95 TBD Call TI Call TI 0 to 70 LM 555CM
LM555CM/NOPB ACTIVE SOIC D 8 95 Green (RoHS & no Sb/Br)
CU SN Level-1-260C-UNLIM 0 to 70 LM 555CM LM555CMM NRND VSSOP DGK 8 1000 TBD Call TI Call TI 0 to 70 Z
LM555CMM/NOPB ACTIVE VSSOP DGK 8 1000 Green (RoHS & no Sb/Br)
CU SN Level-1-260C-UNLIM 0 to 70 Z
LM555CMMX/NOPB ACTIVE VSSOP DGK 8 3500 Green (RoHS & no Sb/Br)
CU SN Level-1-260C-UNLIM 0 to 70 Z
LM555CMX NRND SOIC D 8 2500 TBD Call TI Call TI 0 to 70 LM 555CM LM555CMX/NOPB ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br)
CU SN Level-1-260C-UNLIM 0 to 70 LM 555CM
LM555CN LIFEBUY PDIP P 8 40 TBD Call TI Call TI 0 to 70 LM 555CN LM555CN/NOPB ACTIVE PDIP P 8 40 Green (RoHS & no Sb/Br)
CU SN Level-1-NA-UNLIM 0 to 70 LM 555CN
MC1455P1 LIFEBUY PDIP P 8 40 TBD Call TI Call TI 0 to 70 LM 555CN NE555V LIFEBUY PDIP P 8 40 TBD Call TI Call TI 0 to 70 LM 555CN
(1) (^) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.
(2) (^) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package Type
Package Drawing
Pins SPQ Reel Diameter (mm)
Reel Width W1 (mm)
A
(mm)
B
(mm)
K
(mm)
P
(mm)
W
(mm)
Pin Quadrant
LM555CMM VSSOP DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q
LM555CMM/NOPB VSSOP DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q
LM555CMMX/NOPB VSSOP DGK 8 3500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q
LM555CMX SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q
LM555CMX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q
PACKAGE MATERIALS INFORMATION
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Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LM555CMM VSSOP DGK 8 1000 210.0 185.0 35. LM555CMM/NOPB VSSOP DGK 8 1000 210.0 185.0 35.
LM555CMMX/NOPB VSSOP DGK 8 3500 367.0 367.0 35. LM555CMX SOIC D 8 2500 367.0 367.0 35. LM555CMX/NOPB SOIC D 8 2500 367.0 367.0 35.
PACKAGE MATERIALS INFORMATION
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Pack Materials-Page 2
