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The spring 2000 midterm exam for cs152: computer architecture at the university of california, berkeley. The exam consists of four problems related to digital circuits, critical path analysis, single-cycle processors, and single-cycle datapath design.
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University of California, Berkeley College of Engineering Department of Electrical Engineering and Computer Science Spring 2000 Prof. Bob Brodersen
March 15, 2000 CS152: Computer Architecture This midterm consists of four problems, each of which has multiple parts, so budget your time accordingly. The exam is closed-book, but calculators and one sheet of notes are allowed. Good luck! Name SID Discussion 1 2 3 4 Total
Throughout this problem, use the simple linear delay model presented in class. For the circuit below, assume the following delay parameters: NAND: t (^) plh = 0.5ns, t (^) phl = 0.5ns, t (^) plhf = 0.002ns/fF, t (^) phlf= 0.002ns/fF Input capacitance: 100fF Inverter: t (^) plh = 0.2ns, t (^) phl = 0.2ns, t (^) plhf = 0.001ns/fF, t (^) phlf= 0.001ns/fF Input capacitance: 50fF Wiring Capacitance: (Equal for all nodes) 5fF
a) What is the worst case delay? Assume there is no delay at the inputs X, Y and Z. b) Now assume that you want to generate a symbol for the circuit in part (a). Determine the following parameters for your symbol: t (^) plh, t phl, and the load dependant delay (in ns/fF). X Y F Z
The following MIPS code finds the maximum integer within a bounded array, where $4 contains a pointer to the beginning of the array, $5 contains the length of the array and $3 contains the pointer to store the result at the end. (Assuming there is no branch delay slot.) LW$2,0($4) //assumethefirstnumberisthelargest ADDI$4,$4, ADDI$5,$5,- max: LW$6,0($4)//loadarrayelementandincrementpointer ADDI$4,$4, SLT$7,$2,$6//update$2if$6islarger BEQ$7,$0,next ADD$2,$0,$ next: ADDI$5,$5,-1//continuethesearchuntilendofarray BEQ$5,$0,finish Jmax finish: SW$2,0($3)//storeresult The single-cycle datapath and control unit are shown on the next page. Assume that the delay and energy consumption per operation for each functional unit is as follows: Memory (read or write): 3 ns, 3 pJ ALU and adder: 2 ns, 2 pJ Register file (read or write): 1 ns, 1 pJ All other units: 0 ns, 0 pJ a) What is the minimum clock cycle time for this processor? b) For an array of length N, what is the range of execution time for this program (e.g. the minimum possible execution time and the worst case execution time)? c) What is the energy consumption (per instruction) for each type of instruction in the program? Assume that components are completely turned off and do not consume energy when they are not needed.
Diagram and scratch space for Problem 2:
a) Draw the datapath showing all interconnections and components (including the controller). b) What is the critical path? c) What is the delay of the critical path? d) Show the values of all the control points for each instruction. (The Enable for the PC is given as an example) PCEnable ADDIU 1 ADD 1 SRL 1 Rotate 1
For this problem you will be working with the multi-cycle datapath components on the next page. All inputs for the functional units are labeled, and registers only have one data input and one data output (you should not draw the clock lines). You will not need to deal with control in this problem, so the control inputs to each block are not shown. a) Given the datapath components on the next page, determine the register transfer language description for each of the standard MIPS instructions in the table below. You do not need to fill in every row. Hint: Do not write to the register file at the end of a cycle (i.e. only write directly from a register, not a functional unit). b) You ll notice that some components need to be reused during execution of an instruction. Wire the datapath to support all four instructions, adding only muxes as needed. You may provide constants as inputs to any component. Be sure to label special buses, such as instruction fields. You do not need to draw any control signals (including mux select signals) just assume they will be correctly generated in all cases. c) For each instruction in part (a), calculate the CPI and indicate on the table above which operations occur during each cycle. d) The table below indicates the worst case delay through each of the functional units used in the datapath. Given these delays, calculate the execution time of this processor for a program consisting of 400,000 adds, 250, loads, 250,000 stores, and 100,000 branches. Functional Unit Worst-case Delay Memory 50ns Register File (read) 25ns Register File (write) 15ns ALU 30ns All others 0ns
