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Calculations for various cache memory parameters such as number of bits in physical address, block offset, line number, tag, cache size, main memory size, and tag directory size.
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5 th Semester Advanced Computer Architecture Objectives
Types of microprocessors: Complex instruction set microprocessor: The processors are designed to minimise the number of instructions per program and ignore the number of cycles per instructions. The compiler is used to translate a high-level language to assembly level language because the length of code is relatively short and an extra RAM is used to store the instructions. These processors can do tasks like downloading, uploading and recalling data from memory. Apart from these tasks these microprocessors can perform complex mathematical calculation in a single command. Example: IBM 370/168, VAX 11/78 0 Reduced instruction set microprocessor: These processor are made according to function. They are designed to reduce the execution time by using the simplified instruction set. They can carry out small things in specific commands. These processors complete commands at faster rate. They require only one clock cycle to implement a result at uniform execution time. There are number of registers and less number of transistors. To access the memory location LOAD and STORE instructions are used. Example: Power PC 601, 604, 615, 620 Super scalar microprocessor: These processors can perform many tasks at a time. They can be used for ALUs and multiplier like array. They have multiple operation unit and perform many tasks, executing multiple commands. Application specific integrated circuit: These processors are application specific like for personal digital assistant computers. They are designed according to proper specification. Digital signal multiprocessor: These processors are used to convert signals like analog to digital or digital to analog. The chips of these processors are used in many devices such as RADAR SONAR home theatres etc. Advantages of microprocessor –
To improve the performance of a CPU we have two options:
Throughput = Number of instructions / Total time to complete the instructions So, Throughput = n / (k + n – 1) * Tp Note: The cycles per instruction (CPI) value of an ideal pipelined processor is 1 Problem (example): Consider a pipeline having 4 phases with duration 60, 50, 90 and 80 ns. Given latch delay is 10 ns. Calculate-
There are mainly three types of dependencies possible in a pipelined processor. These are :
1. Structural dependency This dependency arises due to the resource conflict in the pipeline. A resource conflict is a situation when more than one instruction tries to access the same resource in the same cycle. A resource can be a register, memory, or ALU. Example: INSTRUCTION / CYCLE 1 2 3 4 5 I 1 IF(Mem) ID EX Mem I 2 IF(Mem) ID EX I 3 IF(Mem) ID EX I 4 IF(Mem) ID
Let us consider an ADD instruction S, such that S: ADD R1, R2, R Addresses read by S = I(S) = {R2, R3} Addresses written by S = O(S) = {R1} Now, we say that instruction S2 depends in instruction S1, when This condition is called Bernstein condition. Three cases exist:
Types of pipeline
1. Uniform delay pipeline: - In this type of pipeline, all the stages will take same time to complete an operation. - In uniform delay pipeline, Cycle Time (Tp) = Stage Delay - If buffers are included between the stages then, **Cycle Time (Tp) = Stage Delay + Buffer Delay
2. Instruction Pipeline: - In this a stream of instructions can be executed by overlapping fetch, decode and execute phases of an instruction cycle. This type of technique is used to increase the throughput of the computer system. An instruction pipeline reads instruction from the memory while previous instructions are being executed in other segments of the pipeline. Thus we can execute multiple instructions simultaneously. The pipeline will be more efficient if the instruction cycle is divided into segments of equal duration. - In the most general case computer needs to process each instruction in following sequence of steps: o Fetch the instruction from memory (FI) o Decode the instruction (DA) o Calculate the effective address o Fetch the operands from memory (FO) o Execute the instruction (EX) o Store the result in the proper place The flowchart for instruction pipeline is shown below.
Let us see an example of instruction pipeline. Example: Here the instruction is fetched on first clock cycle in segment 1.
A more useful approach is to equip the processor with multiple processing units to handle several instructions in parallel in each processing stage. With this arrangement, several instructions start execution in the same clock cycle and the process is said to use multiple issue. Such processors are capable of achieving an instruction execution throughput of more than one instruction per cycle. They are known as ‘Superscalar Processors’.
An alternative approach to achieving better performance is superpipelining. Superpipelining exploits the fact that many pipeline stages perform tasks that require less than half a clock cycle. A doubled internal clock speed allows those stages to perform two tasks during one external clock cycle. In a superpipelined processor of degree n, the pipeline cycle time is 1/n of the base cycle. Stages that require the full base cycle to complete can be strung into a series of shorter stages, effectively increasing the length of the pipeline and matching the execution latency of each stage. An number of instructions may be in various parts of the execution stage. As a comparison, where an execution operation takes 1