IP Generation and FSK Generation, Study notes of Very large scale integration (VLSI)

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mysinetes C:Asers/Admin/project_lJproject_1.sres/sources_1/new/mysine.v L “timescale Ins / 1p3 2 module mysine(clk, din, dout); 3 dnput clk; 4 input din; =| 3 output signed [10 6 O reg [3:0] count 9,0 always @ (pos clk) a begin 11.0 din) count = count+2? 12/0 count = count + 1; oa € 14 blk_mem_gen_O0 bl(clk, count, dout); pis dmodule ~ |26 mysine.w |i G:/Users/Admin/project_1/project_L.sres/sim_1/new/mysinetest. v L timescale Ins / Ips 2 le mysinetest() ; Ws reg clk, din; 4 wire [ 0] dowt; 5 mysine ml(clk, din, dout); & © inivial 7 begin 80 20 100 110 2 Gep#1000 Sinish; 13 end 14.Q always #10 clk= clk: Wiis endmodule 16 @® mysine.v |G mysinetest.v xX my C:/Users/Admin/Desktop/data.coe i pemory initialization_radix = 10; 2memory initialization width = 11; @") smemory_initialization_vector= 10707, 11383, 120, 13-383, 14-707, 15-824,