HW#13
1. .
𝑡 =𝐶𝑉
2∗𝐼
Here
𝐼 =60
2∗17∗(1.5−0.4)
2+1.5∗(1.5−0.4)
2−1.5
81+0.2∗1.5
2=673.74𝜇𝐴
𝑡 = 𝑅𝐶 = 𝐶𝑉
2∗𝐼
𝑅= 𝑉
2∗𝐼 =1.5
2∗673.74𝜇= 1.11 𝑘 𝑂ℎ𝑚
2.
Delay at node 5 is,
𝑡 =120∗75∗10 +(120+165)∗100∗10 +(120+165)∗95∗10 +(120+165+
105)∗65∗10 +(120+165+105+220)∗200∗10 +120∗15∗ 10+120∗45∗
10 +120∗50∗10 = 225.105 𝑝𝑠
3.
By Charge sharing method
𝑄=(𝐶+𝐶1+𝐶2)𝑉=𝑄
𝑉=𝑄
(𝐶+𝐶1+𝐶2)=125𝑚∗2
125𝑚+20𝑚+8𝑚=1.634
Hence Vo=1.634 V
4.
CMOS logic:
