Design of Control Unit
To execute an instruction, the control unit of the CPU must generate the required control
signal in the proper sequence. As for example, during the fetch phase, CPU has to generate
PCout signal along with other required signal in the first clock pulse. In the second clock pulse
CPU has to generate PCin signal along with other required signals. So, during fetch phase, the
proper sequence for generating the signal to retrieve from and store to PC is PCout and PCin.
To generate the control signal in proper sequence, a wide variety of techniques exist. Most of
these techniques, howeve, fall into one of the two categories,
.1 Hardwired Control
.2 Microprogrammed Control.
Hardwired Control
1. In this hardwired control techniques, the control signals are generated by means of
hardwired circuit. The main objective of control unit is to generate the control signal
in proper sequence.
Consider the sequence of control signal required to execute the ADD instruction that is
explained in previous lecture. It is obvious that eight non-overlapping time slots are
required for proper execution of the instruction represented by this sequence.
Each time slot must be at least long enough for the function specified in the
corresponding step to be completed. Since, the control unit is implemented by
hardwire device and every device is having a propagation delay, due to which it
requires some time to get the stable output signal at the output port after giving the input
signal. So, to find out the time slot is a complicated design task.
2. For the moment, for simplicity, let us assume that all slots are equal in time duration.
Therefore the required controller may be implemented based upon the use of a
counter driven by a clock.
3. Each state, or count, of this counter corresponds to one of the steps of the control
sequence of the instructions of the CPU.
4. By looking into the design of the CPU, we may say that there are various
instruction for add operation. As for example,
ADD NUM R1 Add the contents of memory location specified by NUM
to the contents
of register R1
R1<-R1+[NUM]
ADD R2R1 Add the contents of register R2 to the contents of register R1.
R1<-R1+R2
The control sequence for execution of these two ADD instructions is different. Of
course, the fetch phase of all the instructions remains same.
It is clear that control signals depend on the instruction, i.e., the contents of the
instruction register. It is also observed that execution of some of the instructions
depend on the contents of condition code or status flag register, where the
control sequence depends in conditional branch instruction.
