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An in-depth analysis of mosfets (metal-oxide-semiconductor field-effect transistors), their classification into depletion-type and enhancement-type, and their basic construction and characteristics. It covers topics such as the three terminals (gate, source, and drain), voltage control, unipolar current conduction, and the effects of gate voltage on drain current. The document also discusses the concepts of pinch-off and saturation levels.
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There are three types of FETs: JFETs, MOSFETs, and MESFETs. Further, MOSFETs are classified into depletion type and enhancement-type (D-MOSFET and E-MOSFET).
The field-effect transistor (FET) is a three-terminal device.The three terminals are gate(G), source (S) and Ddrain (D).The FET is voltage controlled device. Just as there are npn and pnp bipolar transistors, there are n-channel and p-channel field effect transistors. The term field effect in the name deserves some explanation. For the FET an electric field is established by the charges present, which controls the conduction path of the output circuit without the need for direct contact between the controlling and controlled quantities. FETs are of three types : the junction field-effect transistor (JFET), the metalāoxideā semiconductor field-effect transistor (MOSFET), and the metal ā semiconductor field-effect transistor (MESFET). The MOSFET category is further broken down into depletion and enhancement ( i.e. D-MOSFET and E=MOSFET). Difference between BJT and FET BJT FET Current controlled device Voltage controlled device Bipolar (current conduction due to flow of holes and electrons) Uniploar (current conduction due to flow of majority charge carriers) Low input impedance as compared to FET High input impedance Ac voltage gain is high Ac voltage gain is low Less temperature stable More temperature stable Larger in size Smaller in size
distribution of the no-bias conditions of Fig. 1. The instant the voltage VDD (= VDS ) is applied, the electrons are drawn to the drain terminal, establishing the conventional current ID with the defined direction of Fig. 2. The path of charge flow clearly reveals that the drain and source currents are equivalent ( ID = IS ). Under the conditions in Fig. 2 , the flow of charge is relatively uninhibited and is limited solely by the resistance of the n - channel between drain and source. It is seen that the depletion region is wider near the top of both p ā type materials. The reason for the change in width of the region is best described through the help of Fig. 3. Assuming a uniform resistance in the n - channel, we can break down Fig. 2. JFET at VGS=0V and VDS>0V Fig.3 Varying reverse-bias potential across the p-n juction of an n-channel JFET the resistance of the channel into the divisions appearing in Fig. 3. The current ID will establish the voltage levels through the channel as indicated on the same figure. The result is that the upper region of the p - type material will be reverse-biased by about 1.5 V, with the lower region only reverse-biased by 0.5 V. The greater the applied reverse bias, the wider is the depletion regionāhence the distribution of the depletion region as shown in Fig. 3. The fact thatthe p ā n junction is reversebiased for the length of the channel results in a gate current of zero amperes, as shown in the same figure. As the voltage VDS is increased from 0 V to a few volts, the current will increase as determined by Ohmās law and the plot of ID versus VDS will appear as shown in Fig. 4.
Fig. 4. ID versus VDS for VGS=0V The relative straightness of the plot reveals that for the region of low values of VDS , the resistance is essentially constant. As VDS increases and approaches a level referred to as VP in Fig. 4 , the depletion regions of Fig. 2 will widen, causing a noticeable reduction in the channel width. The reduced path of conduction causes the resistance to increase and the curve in the graph of Fig. 4 to occur. The more horizontal the curve, the higher the resistance, suggesting that the resistance is approaching āinfiniteā ohms in the horizontal region. If VDS is increased to a level where it appears that the two depletion regions would ātouchā as shown in Fig. 5 , a condition referred to as pinch-off will result. The level of VDS that establishes this condition is referred to as the pinch-off voltage and is denoted by VP , as shown in Fig. 4.
Fig.6 Current source equivalent for VGS=0V, VDS>VP. The choice of notation IDSS is derived from the fact that it is the d rain-to- s ource current with a s hort-circuit connection from gate to source. As we continue to investigate the characteristics of the device we will find that: IDSS is the maximum drain current for a JFET and is defined by the conditions VGS = 0 V and VDS >|VP|. V GS < 0 V The voltage from gate to source, denoted VGS , is the controlling voltage of the JFET. Just as various curves for IC versus VCE were established for different levels of IB for the BJT transistor, curves of ID versus VDS for various levels of V (^) GS can be developed for the JFET. For the n - channel device the controlling voltage VGS is made more and more negative from its VGS = 0 V level. In other words, the gate terminal will be set at lower and lower potential levels as compared to the source.
Fig. 7. Application of anegative voltage to the gate of a JFET. In Fig. 7 a negative voltage of ā 1 V is applied between the gate and source terminals for a low level of VDS. The effect of the applied negative-bias VGS is to establish depletion regions similar to those obtained with V (^) GS = 0 V, but at lower levels of VDS. Therefore, the result of applying a negative bias to the gate is to reach the saturation level at a lower level of VDS , as shown in Fig. 8 for VGS = - 1 V.
MOSFET stands for metal ā oxide ā emiconductor field ā effect transistor. MOSFETs are further broken down into depletion type and enhancement type. The terms depletion and enhancement define their basic mode of operation.
The basic construction of the n - channel depletion-type MOSFET is provided in Fig. 10. A slab of p - type material is formed from a silicon base and is referred to as the substrate. It is the foundation on which the device is constructed. In some cases the substrate is internally connected to the source terminal. However, many discrete devices provide an additional terminal labeled SS , resulting in a four-terminal device. The source and drain terminals are connected through metallic contacts to n - doped regions linked by an n - channel as shown in the figure. The gate is also connected to a metal contact surface but remains insulated from the n - channel by a very thin silicon dioxide (SiO 2 ) layer. SiO 2 is a type of insulator referred to as a dielectric , which sets up opposing (as indicated by the prefix di - ) electric fields within the dielectric when exposed to an externally applied field. The fact that the SiO 2 layer is an insulating layer means that: There is no direct electrical connection between the gate terminal and the channel of a MOSFET.
Fig.10. n-Channel depletion type MOSFET. In addition: It is the insulating layer of SiO 2 in the MOSFET construction that accounts for the very desirable high input impedance of the device. The reason for the label metalāoxideāsemiconductor FET is now fairly obvious: metal for the drain, source, and gate connections; oxide for the silicon dioxide insulating layer; and semiconductor for the basic structure on which the n - and p - type regions are diffused.
Fig. 12. Reduction in free carriers in a channel due to a negative potential at the gate terminal. The resulting level of drain current is therefore reduced with increasing negative bias for VGS , as shown in Fig. 13 for VGS = - 1 V, - 2 V, and so on, to the pinch-off level of - 6 V. The resulting levels of drain current and the plotting of the transfer curve proceed exactly as described for the JFET. Fig. 13. Drain and transfer characteristics for an n-channel depletion type MOSFET.
For positive values of VGS , the positive gate will draw additional electrons (free carriers) from the p - type substrate due to the reverse leakage current and establish new carriers through the collisions resulting between accelerating particles. As the gate-to-source voltage continues to increase in the positive direction, Fig.13 reveals that the drain current will increase at a rapid rate for the reasons listed above. The vertical spacing between the VGS =0 V and VGS = +1 V curves of Fig. 13 is a clear indication of how much the current has increased for the 1-V change in VGS. Due to the rapid rise, the user must be aware of the maximum drain current rating since it could be exceeded with a positive gate voltage. That is, for the device of Fig. 13, the application of a voltage VGS = +4 V would result in a drain current of 22.2 mA, which could possibly exceed the maximum rating (current or power) for the device. As revealed above, the application of a positive gate-to-source voltage has āenhancedā the level of free carriers in the channel compared to that encountered with VGS = 0 V. For this reason the region of positive gate voltages on the drain or transfer characteristics is often referred to as the enhancement region , with the region between cutoff and the saturation level of IDSS referred to as the depletion region.
The basic construction of the n - channel enhancement-type MOSFET is provided in Fig. 14. A slab of p - type material is formed from a silicon base and is again referred to as the substrate. As with the depletion-type MOSFET, the substrate is sometimes internally connected to the source terminal, whereas in other cases a fourth lead (labeled SS) is made available for external control of its potential level. The source and drain terminals are again connected through metallic contacts to n - doped regions, but in Fig. 6.32 the absence of a channel between the two n - doped regions. This is the primary difference between the construction of depletion-type and enhancement-type MOSFETsāthe absence of a channel as a constructed component of the device. The SiO 2 layer is still present to isolate the gate metallic platform from the region between the drain and source, but now it is simply separated from a section of the p - type material. Therefore, we can say that the construction of an enhancement-type MOSFET is quite similar to that of the depletion-type MOSFET, except for the absence of a channel between the drain and source terminals.
Fig. 15. Channel formation in the n-channel enhancement-type MOSFET. The positive potential at the gate will pressure the holes (since like charges repel) in the p - substrate along the edge of the SiO 2 layer to leave the area and enter deeper regions of the p - substrate, as shown in the figure. The result is a depletion region near the SiO 2 insulating layer void of holes. However, the electrons in the p- substrate (the minority carriers of the material) will be attracted to the positive gate and accumulate in the region near the surface of the SiO 2 layer. The SiO 2 layer and its insulating qualities will prevent the negative carriers from being absorbed at the gate terminal. As VGS increases in magnitude, the concentration of electrons near the SiO 2 surface increases until eventually the induced n - type region can support a measurable flow between drain and source. The level of VGS that results in the significant increase in drain current is called the threshold voltage and is given the symbol VT. On specification sheets it is referred to as VGS (Th), although VT is less unwieldy and will be used in the analysis to follow. Since the channel is nonexistent with VGS =0 V and āenhancedā by the application of a positive gate-to-source voltage, this type of MOSFET is called an enhancement-type MOSFET_._ Both depletion- and enhancement-type MOSFETs have
enhancement-type regions, but the label was applied to the latter since it is its only mode of operation. As VGS is increased beyond the threshold level, the density of free carriers in the induced channel will increase, resulting in an increased level of drain current. However, if we hold VGS constant and increase the level of VDS , the drain current will eventually reach a saturation level as occurred for the JFET and depletion-type MOSFET. The leveling off of ID is due to a pinching-off process depicted by the narrower channel at the drain end of the induced channel as shown in Fig. 16. Fig.16. Change in channel and depletion region with increasing level of VDS for a fixed value of VGS. Applying Kirchhoffās voltage law to the terminal voltages of the MOSFET of Fig. 16., we find that
If VGS is held fixed at some value such as 8 V and VDS is increased from 2 V to 5 V, the voltage VDG (by Eq.( 1 )) will increase from ā 6 V to ā 3 V and the gate will become less and less positive with respect to the drain. This reduction in gate-to-drain voltage will in turn reduce the attractive forces for free carriers (electrons) in this region of the induced channel, causing a reduction in the effective channel width. Eventually, the channel will be reduced to the point
2
The equation ( 3 ) shows a nonlinear (curved) relationship between ID and VGS. The k term is a constant that is a function of the construction of the device. The value of k can be determined from the equation ( 4 ),where Don
characteristics of the device.
2 ( ) D on GS on T
Fig. 18. Sketching the transfer characteristics for an n- channel enhancement-type MOSFET from the drain characteristics.
A very effective logic circuit can be established by constructing a p - channel and an n - channel MOSFET on the same substrate as shown in Fig. 1. The induced p - channel on the left and the induced n - channel on the right for the p - and n - channel devices, respectively. The configuration is referred to as a complementary MOSFET or CMOS. It is mostly used as an inverter in digital circuits. as shown in Fig. 2. An inverter is a logic element that āinvertsā the applied signal. That is, if the logic levels of operation are 0 V (0-state) and 5 V (1-state), an input level of 0 V will result in an output level of 5 V, and vice versa. In Fig. 2 both gates are connected to the applied signal and both drain to the output Vo. The source of the p - channel MOSFET ( Q 2 ) is connected directly to the applied voltage VSS , whereas the source of the n - channel MOSFET ( Q 1 ) is connected to ground. For the logic levels defined above, the application of 5 V at the input should result in approximately 0 V Fig. 1. CMOS with applied voltage to different terminal. at the output. With 5 V at Vi (with respect to ground), VGS 1 = Vi , and Q 1 is āon,ā resulting in a relatively low resistance between drain and source as shown in Fig. 3. Since Vi and VSS are at 5 V, VGS 2 = 0 V, which is less than the required VT for the device, resulting in an āoffā state. The resulting resistance level between drain and source is quite high for Q 2 , as shown in Fig. 3. A simple application of the voltage-divider rule will reveal that Vo is
