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DPSD digital principle and system designDPSD digital principle and system designDPSD digital principle and system designv
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T flip – flop is also known as “Toggle Flip – flop”. The flip – flop acts as a Toggle switch. Toggling means ‘Changing the next state output to complement of the present state output’. The T flip – flop can be designed by making simple modifications to the JK flip – flop. The T flip – flop is a single input device and hence by connecting J and K inputs together and giving them with single input called T, thus a JK flip – flop is converted into T flip – flop. Case (i) T=0 , Qn=0, Qn’= Gate 3, input are T= 0 , Qn’=1, C=1, therefore Gate3 output is 1 Gate 4 input are T= 0 , Qn=0, C=1, Therefore Gate 4 output is 1 A input of 1 1 in SR latch means no change, so Qn+1= 0 and Qn+1’= 1 T= 0 , Qn= 1 , Qn’= 0 Gate 3, input are T= 0 , Qn’= 0 , C=1, therefore Gate3 output is 1 Gate 4 input are T= 0 , Qn= 1 , C=1, Therefore Gate 4 output is 1 A input of 10 in SR latch means No Change, so Qn+1= 1 and Qn+1’= 0
Case (ii) T= 1 , Qn=0, Qn’= Gate 3, input are T= 1 , Qn’=1, C=1, therefore Gate3 output is 0 Gate 4 input are T= 1 , Qn=0, C=1, Therefore Gate 4 output is 1 A input of 1 1 in SR latch means Set, so Qn+1= 1 and Qn+1’= 0 T= 1 , Qn= 1 , Qn’= 0 Gate 3, input are T=1, Qn’= 0 , C=1, therefore Gate3 output is 1 Gate 4 input are T=1, Qn= 1 , C=1, Therefore Gate 4 output is 0 A input of 10 in SR latch means Reset, so Qn+1= 0 and Qn+1’= 1 Truth Table T Qn Qn’ Qn+1 Qn+1’ 0 0 1 0 1 0 1 0 1 0 1 0 1 1 0 1 1 0 0 1 Reduced Truth Table: Also Excitation Table (Write Excitation table below characteristic equation) Qn T Qn+ 0 0 0 1 0 1 0 1 1 1 1 0 When the value of T =1 the toggling occurs between present state and next state. Qn+1=T’Qn+TQn’