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Introduction to VHDL

Dr. Binu Paul

CUSAT

Intro to VHDL 2

-- VHDL

VHSIC Hardware

Description Language

VHSIC --

Very High Speed Integrated Circuits

Dr Binu Paul

Intro to VHDL 4

VHDL --

VHDL is a programming language that allows one

to model and develop complex digital systems in a

dynamic environment.

It is technology/vendor independent

It describes a logic circuit by a function

expression, a data flow and /or a structure

From this coded description a hardware logic

circuit can be inferred by the compiler/synthesiser

Allows to designate in/out ports (bits) and specify

behavior or response of the system.

Dr Binu Paul

Intro to VHDL 5

Basic Design Methodology

Requirements

Model Simulate

Gate-level

Model

Synthesize

Simulate Test Bench

ASIC or FPGA

Place & Route

Timing

Model

Simulate

Dr Binu Paul

VHDL design flow

Dr Binu Paul Intro to VHDL 7

VHDL Program structure

Dr Binu Paul Intro to VHDL 8

Library Declaration

Gives a list of all libraries the compiler will need

to process the design code

‘ WORK ' is a default library which gets included

in the project tree of a design and holds all

compiled files in every project created in the EDA

tool

A library has some definitions , packages, entity –

architecture pairs etc

Dr Binu Paul Intro to VHDL 10

Library Declaration

IEEE standardised a library containing some

data types (like boolean, decimal, hexadecimal, character etc),

basic entities (like and,nand,xor etc),

functions

in their IEEE_STD no 1164

This in invoked in project as

library ieee ;

use ieee.std_logic_1164.all;

Use clause is included to invoke a particular package in the

specified library

This package has predefined

• Logic functions [like AND, OR, XOR, XNOR, NOT]
• Signal types [see next slide]
• constant types [integer and real]

Dr Binu Paul Intro to VHDL 11

ENTITY Declaration

The basic

design

element in

Dr Binu Paul Intro to VHDL 13

Intro to VHDL 14

Jumping right in to a Model –

Modeling Interfaces

Entity declaration

describes the input/output ports of a module

entity add2 is

port ( a0, a1, b0, b1,cin, en : in std_logic ;

Sout: out std_logic_vector ( 3downto 0 ) );

end add2;

entity name port names port mode (direction)

port type

reserved words

punctuation

Dr Binu Paul

Architecture Modelling

(functionality can be described in different ways

Dr Binu Paul Intro to VHDL 17

Intro to VHDL 18

Basic VHDL Concepts

Interfaces -- i.e. ports

Behavior

Structure

Test Benches

Analysis, simulation

Synthesis

But VHDL is NOT C ...

There are some similarities, as with any

programming language, but syntax and logic are

quite different; so get over it !!

Dr Binu Paul

Intro to VHDL 20

Jumping right in to a Model –

Modeling Interfaces

Entity declaration

describes the input/output ports of a module

entity add2 is

port ( a0, a1, b0, b1,cin, en : in std_logic ;

Sout: out std_logic_vector ( 3downto 0 ) );

end add2;

entity name port names port mode (direction)

port type

reserved words

punctuation

Dr Binu Paul

Intro to VHDL 21

Jumping right in to a Model –

Modeling Interfaces

Dr Binu Paul

Architecture body

describes an implementation of an entity

may be several per entity