Student'Name,'Surname'and'Number:'''''''''''
CSE315-Make,up-2015,,,,,Make,up,Exam,,,,,,Date:,,27/01/16,
GSM'phones'are'not'allowed.'The'lecture'notes,'books'and'calculators'can'be'used.'All'the'answers'must'be'clearly'stated;'otherwise'no'''partial'
credit'will'be'given.'The'exam'duration'is'110'minutes.'
,
1.,A,logic,circuit,has,four,inputs:,a3,,a2,,a1,,a0,,representing,the,BCD,number,A,=,(a3,a2,a1,a0)2,,and,,one,
output:,y,,satisfying,the,following,(25,pts):,
,
y=
0,
1,
dc,
⎧
⎨
⎪
⎩
⎪
if
if
if
A≤4,
5≤A≤9,
A≥10.
,
,,,
(Note:,dc,represents,“don’t,care”,values.),,
a) Find,the,simplified,sum,of,products,expression,for,y,,and,draw,the,circuit,diagram.,,
b) Implement,the,circuit,using,an,8x1,Mux.,
,
,
2.,,ASCII,characters,are,sent,sequentially,to,the,circuit,below.,If,“OK”,is,sent,(first,“O”,then,in,the,next,sequence,“K”),,
the,output,(y),becomes,1,and,stays,as,1,afterwards;,otherwise,the,output,stays,as,0.,(If,desired,,a,clear,input,(for,all,
flip-flops),can,be,used,to,reset,the,system.),(40,pts),
,
y
clk
x7
x6
x5
x4
x3
x2
x1
x0
,
,
Design,the,required,system,using,D,flip-flops.,
,
Note:,,,ASCII,codes:,,“O”:,0x48,,,“K”:,0x4B.,
,
3. A sequence detector with one bit input X and one bit output Z,which has the input/output definitions below:, ,
,
,
,
,
,
,
,
,
Reset,and,Clock,signals,are,one,bit.,The,detector,should,recognize,the,input,(X),sequence,“101”.,The,
detector,should,keep,checking,for,the,appropriate,sequence,and,should,not,reset,to,the,initial,state,after,it,
has,recognized,the,sequence.,The,detector,initializes,to,a,reset,state,when,input,,RESET,is,activated.,For,
example,,for,input,X,=,“…110110101…”,,output,become,Z,=,“…000100101…”,
a) Design,the,synchronous,sequential,circuit,and,give,the,circuit,diagram.,(15,pts),
b) Write,the,Verilog,code,for,the,sequence,detector.,(use,always,blocks,,if/else,statements,,case,
statements),(25,pts),
,
Finite,State,
Machine,
X,
Z,
reset,
clock,