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Problem No. 1
In a certain chemical – processing plant, a liquid chemical is used in a
Manufacturing process. The chemical is stored in three different tanks. A level
sensor in each tank produces a HIGH voltage when the level of chemical in the
tank drops below a specified point.Design a circuit that monitors the chemical
level and indicate when the level inany two of the tanks drops below the specified
point.Draw the circuit using NAND – AND two level implementation.
Solution:
In the following Truth Table 1 is representing a drop in the liquid level in some tank (A, B or C).
In the following Truth Table 0 is representing normal liquid level in some tank (A, B or C).
When in a combination two 1 come, then there should be an alarm. Alarm would be activated by high
voltage ( my assumption ).
A B C OUTPUT OF SENSOR
0 1 1 1(Alarm) 1 0 0 0 1 0 1 1(Alarm) 1 1 0 1(Alarm) 1 1 1 1(Alarm)
The required form is NAND – AND, which is Product of Sums. So we will combine zeroes in K-map to obtain F’.
F’ = A’B’+A’C’+B’C’
F= (A+B).(A+C).(B+C)
QUESTION NO.
In a simple copy machine, a stop signal s is to be generated to stop the
machine’s operation and energizing an indicator light whenever either of the
following condition exists: (1) There is no paper in the paper feeder tray or (2) the
two micro switches in the paper path are activated, indicating a jam in the paper
path. The presence of paper in the feeder tray is indicated by a HIGH at logic
signal P. Each of the micro switches produces a logic signal (Q & R) that goes
HIGH whenever a paper is passing over the switch to activate it. Design the logic
Figure 1 Implementation of above expression of F
Figure 2 NAND-AND Implementation of F
QUESTION NO.
Professor Ali computes grades as follows: He uses only the first digit (that
Is, 9 for averages between 90 and 99). He never has an average of 100. He gives P
(Pass) to anyone with an average of 60 or above and an F to anyone with an
average below 60. That first digit is coded in 8421 code (that is, straight binary, 5
as 0101, for example); these are inputs w, x, y, and z. Give the truth table of the
problem. Implement the circuit using decoder and logic gates
W, X, Y, Z represents binary value of last digit of average. Digit Above or equal to 10 is don’t care condition as it can never happen.
Truth Table for the given problem is
W X Y Z f 0 0 0 0 0(FAIL) 0 0 0 1 0(FAIL) 0 0 1 0 0(FAIL) 0 0 1 1 0(FAIL) 0 1 0 0 0(FAIL) 0 1 0 1 0(FAIL) 0 1 1 0 1(PASS) 0 1 1 1 1(PASS) 1 0 0 0 1(PASS) 1 0 0 1 1(PASS) 1 0 1 0 X 1 0 1 1 X 1 1 0 0 X 1 1 0 1 X 1 1 1 0 X 1 1 1 1 X
Function is 1(PASS) at minterms 0,1,2,3,4,
Function is 1(PASS) at minterms 6,7,8,
QUESTION NO.
The system is a speed warning device. It receives, on two lines, an indication of
thespeed limit on the highway. There are three possible values 45, 55, or 65 MPH.
Itreceives from the automobile, on two other lines, an indication of speed of the
vehicle.There are four possible values under 45, between 46 and 55, between 56
and 65, andover 65 MPH. It produces two outputs. The first f, indicates whether
the car is goingabove the speed limit. The second g, indicates that the car is
driving at “dangerous speed”– defined as either over 65 MPH or more than 10
MPH above the speed limit. Show howeach of the inputs and outputs are coded (
in terms of binary values ) and complete thetruth table for the system. Design the
system using appropriate size of multiplexers.
Solution:
A and B are inputs from Car speed
A B x(Speed) 0 0 x< 45 mph 0 1 46<x<55mph 1 0 56<x<65mph 1 1 x>65mph C and D are inputs from Speed Limit
C D X(Speed limit) 0 0 X=45mph 0 1 X=55mph 1 0 X=65mph 1 1 Don’t care
Truth Table for the given problem is
QUESTION NO.
Design an Error Coding and Decoding System. A data coder/decoder system
block diagram is given below as figure P5. We have 3 bit of information to be
coded andtransmitted. We will code these into 5-bit work, where the first 3 bits
are just theinformation. The fourth bit is chosen such that there is an odd number
of ones in bit 1,3and 4. The fifth bit is chosen such that there is an odd number of
ones in bits 2,3 and 5.When the five bits are transmitted, an error may occur
during that transmission.We will design the system under the assumption that at
most one error occurs in a 5-bitword. We will design the decoder circuit that
takes the 5-bit word (possibly containing anerror) – call the bits a,b,c,d,e and
produces one of the words that it could have been – callthe answer p,q,r. In
addition there are two outputs to indicate how sure we are that theanswer is
correct. Output f is 1 if the received word is same as one of the transmittedwords
(that is , no errors were made); and output g is 1 if the answer is the only data
thatcould have resulted from no errors or a single error. As we will see, a single
error in twodifferent transmitted words may result in the same received word.
Solution:
Coding mechanism
When no. of 1 in Y and Z is ODD then w will become 0 so that no. of 1 in w, y and z remain ODD.
When no. of 1 in Y and Z is EVEN then w will become 1 so that no. of 1 in w, y and z remain ODD.
In this case use of XNOR gate would be feasible as it gives 1 when input contains even no. of 1’s otherwise it gives 0 at output.
Similarly we will code x, z and v
Coding block
De-Coding mechanism
In ideal condition at the receiving end if d is 1 then it means a and c are EVEN (f’ would be 1).So for no- error circumstances d and f’ would be same. It will make f1=1. Similarly f2 would also be 1 in case of no error. If total transmission system is error free then f1 and f2 would be 1 at the same time making f equals to 1. So f would be 1 if there is no error occurs during transmission.
DECODING BLOCK
QUESTION NO.
Design a system to produce display of directions. It uses seven-segment display
asshown below. A 1 on line g for example lights segment g.The sequence of
display is controlled by a two bit counter which counts in asequence of 11, 10, 00
ans 01. The input code decide the display as follows
Code Direction
00 Left
01 Right
10 Up
11 Down
Design the Combinational circuit for the display 2 X 4 decoder and appropriate
logic
gates.
Solution:
Truth Table for the given problem is (Led needs HIGH logic to emit light)
A B a b C d e f g 0 0 LEFT 0 0 0 1 1 1 0 0 1 RIGHT 1 1 1 0 1 1 1 1 0 UP 0 1 1 1 1 1 0 1 1 DOWN 1 1 1 1 1 1 0 Some facts obvious from table are following:
a = B……………( sum of 2nd^ and 4th^ minterm)
b = A+B……….(sum of 2nd,3rd^ and 4th^ minterm)
c = A+B……….(sum of 2nd,3rd^ and 4th^ minterm)
g = A’.B……. (2nd^ minterm)
d = A+B’……..(complement of g)
e = 1……………(Always 1)
f = 1……………(Always 1)
As output of decoder is a minterm. So we OR the required minterms to obtain output of particular LED.
