RAKESH ASERY(09EC73)
OBJECT:-Design Full Adder using appropriate software like VHDL (xilinx).
Full Adder CODING :-
entity RAFADDER is
Port ( A : in std_logic;
B : in std_logic;
C : in std_logic;
SUM : out std_logic;
CARRY : out std_logic);
end RAFADDER;
architecture Behavioral of RAFADDER is
begin
SUM <= A XOR B XOR C;
CARRY <= (A AND B) OR (B AND C) OR (C AND A);
end Behavioral;
SCHEMETIC DIAGRAM OF SUM :-
