Design 8to1Multiplexer using appropriate software like VHDL (xilinx)., Assignments of Verilog and VHDL

RAKESH ASERY(09EC73)

OBJECT :-Design 8to1Multiplexer using appropriate software like VHDL (xilinx).

8to1Multiplexer CODING :-

entity RA81MUX is

Port ( I : in std_logic_vector(7 downto 0);

S : in std_logic_vector(2 downto 0);

O : out std_logic);

end RA81MUX;

I(4) when "100",

I(3) when "011",

I(2) when "010",

I(1) when "001",

I(0) when "000",

I(0) when others;

end Behavioral;

SCHEMATIC DIAGRAM :-