RAKESH ASERY(09EC73)
OBJECT :-Design 1t4 Demultiplexer using appropriate software like VHDL
(xilinx).
1to4Demultiplexer CODING :-
entity RA41DMUX is
Port ( I : in std_logic;
S : in std_logic_vector(1 downto 0);
W0 : out std_logic;
W1 : out std_logic;
W2 : out std_logic;
W3 : out std_logic);
end RA41DMUX;
architecture Behavioral of RA41DMUX is
begin
W3 <= I when S="11";
W2 <= I when S="10";
W1 <= I when S="01";
W0 <= I when S="00";
end Behavioral;
SCHEMATIC DIAGRAM :-
