Design 16to1Multiplexer using appropriate software like VHDL, Assignments of Verilog and VHDL

RAKESH ASERY(09EC73)

OBJECT :-Design 16to1Multiplexer using appropriate software like VHDL

(xilinx).

16to1Multiplexer CODING :-

entity RA16TO1MUX is

Port ( W : in std_logic_vector(15 downto 0);

S : in std_logic_vector(3 downto 0);

F : out std_logic);

F <= W(15) when "1111",

W(14) when "1110",

W(13) when "1101",

W(12) when "1100",

W(11) when "1011",

W(10) when "1010",

W(9) when "1001",

W(8) when "1000",

W(7) when "0111",

W(6) when "0110",

W(0) when others;

end Behavioral;