Quiz 2 – solution
A synchronous sequential circuit has to be designed using two D flip-flops and logic gates to create
the two cyclic sequences given below depending on the value of the Mode input M.
Q1 Q0 = 00
→
01
→
11
→
10
→
00…… if M = 0, and Q1 Q0 = 00
→
10
→
11
→
01
→
00…… if M = 1,
where Q1 and Q0 are the Q-outputs of the two flip-flops. The circuit must also have a synchronous
Reset input R that would make Q1 Q0
00 at the next active clock edge from any other state.
(a) Construct the State Diagram of the circuit, denoting the four states by 00, 01, 10 and 11 and
indicating the values of the two inputs R and M for every transition, given that the circuit has
no separate output other than the state variables. [4]
(a) Write down the State Table of the circuit for R = 0, with the columns as shown below: [4]
Q1
Q0
M
Q1(t+1)
Q0(t+1)
0
0
0
0
1
0
0
1
1
0
0
1
0
1
1
0
1
1
0
0
1
0
0
0
0
1
0
1
1
1
1
1
0
1
0
1
1
1
0
1
(b) Hence obtain the Boolean expressions for D1 and D0 in terms of Q1, Q0, R and M. [2]
If R = 1, Q1(t+1) = 0 and Q0(t+1) = 0, and hence R’ has to be a common factor of D1 and D0.
D1 = Q1(t+1) = Q1’•Q0’•R’•M + Q1’•Q0•R’•M’ + Q1•Q0’•R’•M + Q1•Q0•R’•M’,
D0 = Q0(t+1) = Q1’•Q0’•R’•M’ + Q1’•Q0•R’•M’ + Q1•Q0’•R’•M + Q1•Q0•R’•M.
Simpler expressions (not necessary):
D1 = Q1(t+1) = Q0’•R’•M + Q0•R’•M’,
D0 = Q0(t+1) = Q1’•R’•M’ + Q1•R’•M.
10,11 10,11,01
0 0 0 1
00
10,11,00 10,11 00 01
01 00
1 0 1 1
01
