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Quiz 3 Solution: Analyzing Control Bits & Memory Ops in Single Bus - Prof. Biswas, Quizzes of Digital Electronics

The solution to quiz 3, which involves analyzing the active control bits and memory operations in a single bus architecture. The solution includes the actions taken in each clock cycle, the values of the register contents, and the identification of the data memory location and its contents after clock no. 19.

Typology: Quizzes

2020/2021

Uploaded on 12/23/2022

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Quiz 3 solution
The table given below lists the ACTIVE CONTROL BITS observed in the clock cycles excluding the
FETCH cycles, when a particular program is run.
(a) Using the given documentation of the Single Bus Architecture, write down the action giving
numerical values of the Register contents for each of the 11 listed clock cycles. [6]
(b) Find the values of the contents of the Registers R0 and R2 after clock no. 19. [2]
(c) Identify the Data Memory location used in the program and the contents of that memory
location after clock no. 19. [2]
(a) The missing Clock nos. correspond to the FETCH cycles. Hence Clock nos. 2, 4, 6, 17 and 19
correspond to instructions having no READ cycle, whereas the consecutive clock nos. 8-9, 11-
12 and 14-15 correspond to instructions having both READ and EXECUTE cycles. [6]
Clock
Active Control Bits
Action
2
SPC, RD, LRN, IPC, SIF (<rn> = 0, <od> = 00H)
[R0] <od> = 00 (MVI R0)
4
SPC, RD, LRN, IPC, SIF (<rn> = 1, <od> = 40H)
[R1] <od> = 40 (MVI R1)
6
ER0, LRN (<rn> = 2)
[R2] [R0] = 00 (MVD R2)
8
ERN, LOR (<rn> = 2)
[OR] [R2] =
00/01/02/03
INC R2
9
EOR, SAL, LRN, SIF (<af> = 4)
[R2] A + 1
= [OR] + 1 =
01/02/03/04
11
ER0, LOR
[OR] [R0] =
00/40/80/C0
ADA R1
12
ERN, SAL, LR0, SIF (<af> = 8, <rn> = 1)
[R0] A + B
= [OR] + [R1] =
40/80/C0/00 (C = 1)
14
SPC, RD, LOR, IPC, EFL, SIF (<fl> = 3, <od> = 05H)
[OR] <od> = 05,
FETCH if <fl> = NC = 0
JCD NC 05H
15
EOR, LPC, SIF
[PC] [OR] = 05
17
ERN, LR0 (<rn> = 1)
[R0] [R1] = 40 (MVS R1)
19
ERN, WR, SIF (<rn> = 2)
[[R0]] = [40] [R2] (STA R2)
(b) The instruction at clock 14 is a conditional Jump, which creates a loop comprising the
instructions from clock 6 (following clock 5 which is the Fetch for the action at clock 60) to
clock 12. The loop keeps running as long as the result of the addition done at clock 12 does
not force CARRY = 1. Each pass of the loop increases [R0] by 40H, and hence CARRY 1 after
4 passes of the loop. After clock 17, therefore, [R0] = 40H and [R2] = 4. [2]
(c) The last instruction (STA R2) at clock 19 addresses memory location [R0] = 40H and stores the
value [R2] = 4 in that memory location. [2]

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Quiz 3 – solution The table given below lists the ACTIVE CONTROL BITS observed in the clock cycles excluding the FETCH cycles, when a particular program is run. (a) Using the given documentation of the Single Bus Architecture, write down the action giving numerical values of the Register contents for each of the 11 listed clock cycles. [6] (b) Find the values of the contents of the Registers R 0 and R 2 after clock no. 19. [2] (c) Identify the Data Memory location used in the program and the contents of that memory location after clock no. 19. [2] (a) The missing Clock nos. correspond to the FETCH cycles. Hence Clock nos. 2, 4, 6, 17 and 19 correspond to instructions having no READ cycle, whereas the consecutive clock nos. 8 - 9 , 11 - 12 and 14- 15 correspond to instructions having both READ and EXECUTE cycles. [6] Clock Active Control Bits Action 2 SPC, RD, LRN, IPC, SIF ( = 0, = 00H) [R0]  = 00 (MVI R0) 4 SPC,^ RD, LRN, IPC,^ SIF^ ( =^ 1,^ = 40H)^ [R^1 ]^ ^ =^40 (MVI R1) 6 ER 0 , LRN ( = 2) [R2]  [R0] = 00 (MVD R2) 8 ERN, LOR ( = 2)

[OR]  [R2] =

INC R

9 EOR, SAL, LRN,^ SIF^ ( = 4)

[R2]  A + 1

= [OR] + 1 =

11 ER 0 , LOR

[OR]  [R0] =

00 /40/80/C

ADA R

12 ERN, SAL, LR 0 , SIF ( = 8, = 1)

[R 0 ]  A + B

= [OR] + [R 1 ] =

40 /80/C0/00 (C = 1)

14 SPC, RD, LOR, IPC, EFL, SIF ( = 3, = 05H) [OR]  = 05, FETCH if = NC = 0 (^) JCD NC 05H 15 EOR, LPC, SIF [PC]^ ^ [OR] = 0^5 17 ERN, LR 0 ( = 1) [R 0 ]  [R1] = 40 (MVS R1) 19 ERN, WR, SIF ( = 2) (^) [[R0]] = [40]  [R 2 ] (STA R2) (b) The instruction at clock 14 is a conditional Jump, which creates a loop comprising the instructions from clock 6 (following clock 5 which is the Fetch for the action at clock 60) to clock 12. The loop keeps running as long as the result of the addition done at clock 1 2 does not force CARRY = 1. Each pass of the loop increases [R0] by 40H, and hence CARRY  1 after 4 passes of the loop. After clock 17, therefore, [R0] = (^40) H and [R2] = 4. [2] (c) The last instruction (STA R2) at clock 19 addresses memory location [R0] = (^40) H and stores the value [R2] = 4 in that memory location. [2]