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Counter Circuit -Components and Design Techniques for Digital System - Exams, Exams of Digital Systems Design

Main points of this past exam are: Counter Circuit, Minimum Number, Schematic Diagram, Code Converter, Full Adder, Characteristic Table, Inputs Together, Reduced Flow, Flow Table, Primitive Flow

Typology: Exams

2012/2013

Uploaded on 04/02/2013

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Your Name: __________________________ SID Number: _______________________
Quiz 2 Page 1 of 6 CS 150 - Sp. 97
BERKELEY
• DAVIS
• IRVINE
• LOS ANGELES
• RIVERSIDE
• SAN DIEGO
• SAN FRANCISCO
UNIVERSITY OF CALIFORNIA AT BERKELEY
SANTA BARBARA
Department of Electrical Engineering
and Computer Sciences CS 150 - Spring 1997
Prof. A. R. Newton
Quiz 2
Room 10 Evans Hall, 2:10pm Tuesday April 8th
(Open Katz only, Calculators OK, 1hr 20mins)
Include all final answers in locations indicated on these pages and in pen. Use space provided for all working. If necessary, attach
additional sheets by staple at the end. BE SURE TO WRITE YOUR NAME ON EVERY SHEET.
1. (a) Convert the BCD coded number below to equivalent decimal form:
1000011101100010.01100101
(b) Convert (271.A)16 to (i) Base 2 and (ii) Base 8 equivalents.
(c) Design a circuit for converting a 4-bit Gray code into its binary equivalent. You may use
AND, OR, XOR, or
inverter gates only. Use as few gates as possible.
(d) Implement a 1-bit full adder using a minimum number of 4-input, two control-line
multiplexers and inverters
only. An inverter counts as 1/5th (20%) of a MUX. Assume complements are not available.
1 (a) (10pts)
1000011101100010.01100101BCD = ___________________10
(b) (10pts)
(271.A)16 = ______________2
______________8
(c) (10pts) Schematic diagram of code converter:
(d) (10pts) Schematic diagram of 1-bit full adder:
(1) /40
(2) /40
(3) /60
TOTAL /140
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Your Name: __________________________ SID Number: _______________________

Quiz 2 Page 1 of 6 CS 150 - Sp. 97

BERKELEY • DAVIS • IRVINE • LOS ANGELES • RIVERSIDE • SAN DIEGO • SAN FRANCISCO

UNIVERSITY OF CALIFORNIA AT BERKELEY SANTA BARBARA • SANTA CRUZ Department of Electrical Engineering and Computer Sciences

CS 150 - Spring 1997 Prof. A. R. New ton

Quiz 2

Room 10 Evans Hall, 2:10pm Tuesday April 8th

(Open Katz only, Calculators OK, 1hr 20mins)

Include all final answers in locations indicated on these pages and in pen. Use space provided for all working. If necessary, attach additional sheets by staple at the end. BE SURE TO WRITE YOUR NAME ON EVERY SHEET.

  1. (a) Convert the BCD coded number below to equivalent decimal form:

(b) Convert (271.A) 16 to (i) Base 2 and (ii) Base 8 equivalents. (c) Design a circuit for converting a 4-bit Gray code into its binary equivalent. You may use AND, OR, XOR, or inverter gates only. Use as few gates as possible. (d) Implement a 1-bit full adder using a minimum number of 4-input, two control-line multiplexers and inverters only. An inverter counts as 1/5th^ (20%) of a MUX. Assume complements are not available.

1 (a) (10pts)

1000011101100010.01100101BCD = ___________________ 10

(b) (10pts) (271.A) 16 = ______________ 2

______________ 8

(c) (10pts) Schematic diagram of code converter:

(d) (10pts) Schematic diagram of 1-bit full adder:

TOTAL /

  • CS 150 - Sp. 97 Page 2 of 6 Quiz
    • Additional space for Problem

CS 150 - Sp. 97 Page 4 of 6 Quiz 2

(ii) (10pts) Proof of characteristics with two inputs connected:

Additional space for Problem 2

Your Name: __________________________

Quiz 2 Page 5 of 6 CS 150 - Sp. 97

(3) As usual, for the following problems, be sure to state all assumptions clearly.

(a) Obtain the reduced flow table for the primitive flow table shown opposite.

(b) Obtain the primitive flow table for a negative edge-triggered T flip-flop. Consider T as a regular input, C as its clock input, and Q as its output. Do not merge the table.

3(a) (10pts)Reduced Flow table:

(b) (20pts) Primitive flow table for edge-triggered T flip-flop:

Continued on following page