computer science and engineering data communication, Exams of Data Communication Systems and Computer Networks

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Module

Data Link control

Lesson

Error Detection and

Correction

a retransmission. The former strategy uses Error-Correcting Codes and latter uses Error-detecting Codes.

To understand how errors can be handled, it is necessary to look closely at what error really is. Normally, a frame consists of m-data bits (i.e., message bits) and r-redundant bits (or check bits). Let the total number of bits be n (m + r). An n-bit unit containing data and check-bits is often referred to as an n-bit codeword.

Given any two code-words, say 10010101 and 11010100, it is possible to determine how many corresponding bits differ, just EXCLUSIVE OR the two code-words, and count the number of 1’s in the result. The number of bits position in which code words differ is called the Hamming distance. If two code words are a Hamming distance d-apart, it will require d single-bit errors to convert one code word to other. The error detecting and correcting properties depends on its Hamming distance.

• To detect d errors, you need a distance (d+1) code because with such a code there is no way that d-single bit errors can change a valid code word into another valid code word. Whenever receiver sees an invalid code word, it can tell that a transmission error has occurred.
• Similarly, to correct d errors, you need a distance 2d+1 code because that way the legal code words are so far apart that even with d changes, the original codeword is still closer than any other code-word, so it can be uniquely determined.

First, various types of errors have been introduced in Sec. 3.2.2 followed by different error detecting codes in Sec. 3.2.3. Finally, error correcting codes have been introduced in Sec. 3.2.4.

3.2.2 Types of errors

These interferences can change the timing and shape of the signal. If the signal is carrying binary encoded data, such changes can alter the meaning of the data. These errors can be divided into two types: Single-bit error and Burst error.

Single-bit Error The term single-bit error means that only one bit of given data unit (such as a byte, character, or data unit) is changed from 1 to 0 or from 0 to 1 as shown in Fig. 3.2.1.

Single bit change (1 is changed to 0)

Received

Sent

Figure 3.2.1 Single bit error

Single bit errors are least likely type of errors in serial data transmission. To see why, imagine a sender sends data at 10 Mbps. This means that each bit lasts only for 0.1 μs (micro-second). For a single bit error to occur noise must have duration of only 0.1 μs (micro-second), which is very rare. However, a single-bit error can happen if we are having a parallel data transmission. For example, if 16 wires are used to send all 16 bits of a word at the same time and one of the wires is noisy, one bit is corrupted in each word.

Burst Error The term burst error means that two or more bits in the data unit have changed from 0 to 1 or vice-versa. Note that burst error doesn’t necessary means that error occurs in consecutive bits. The length of the burst error is measured from the first corrupted bit to the last corrupted bit. Some bits in between may not be corrupted.

Bits in error

Length of burst (6 bits)

Received

Sent

Figure 3.2.2 Burst Error

Burst errors are mostly likely to happen in serial transmission. The duration of the noise is normally longer than the duration of a single bit, which means that the noise affects data; it affects a set of bits as shown in Fig. 3.2.2. The number of bits affected depends on the data rate and duration of noise.

3.2.3 Error Detecting Codes

Basic approach used for error detection is the use of redundancy, where additional bits are added to facilitate detection and correction of errors. Popular techniques are:

• Simple Parity check
• Two-dimensional Parity check
• Checksum
• Cyclic redundancy check

Table 3.2.1 Possible 4-bit data words and corresponding code words

Decimal value Data Block Parity bit Code word 0 0000 0 0000 0 1 0001 1 0001 1 2 0010 1 0010 1 3 0011 0 0011 0 4 0100 1 0100 1 5 0101 0 0101 0 6 0110 0 0110 0 7 0111 1 0111 1 8 1000 1 1000 1 9 1001 0 1001 0 10 1010 0 1010 0 11 1011 1 1011 1 12 1100 0 1100 0 13 1101 1 1101 1 14 1110 1 1110 1 15 1111 0 1111 0

Note that for the sake of simplicity, we are discussing here the even-parity checking, where the number of 1’s should be an even number. It is also possible to use odd-parity checking, where the number of 1’s should be odd.

Performance An observation of the table reveals that to move from one code word to another, at least two data bits should be changed. Hence these set of code words are said to have a minimum distance ( hamming distance ) of 2, which means that a receiver that has knowledge of the code word set can detect all single bit errors in each code word. However, if two errors occur in the code word, it becomes another valid member of the set and the decoder will see only another valid code word and know nothing of the error. Thus errors in more than one bit cannot be detected. In fact it can be shown that a single parity check code can detect only odd number of errors in a code word.

3.2.3.2 Two-dimension Parity Check

Performance can be improved by using two-dimensional parity check, which organizes the block of bits in the form of a table. Parity check bits are calculated for each row, which is equivalent to a simple parity check bit. Parity check bits are also calculated for all columns then both are sent along with the data. At the receiving end these are compared with the parity bits calculated on the received data. This is illustrated in Fig. 3.2.4.

Figure 3.2.4 Two-dimension Parity Checking

Performance Two- Dimension Parity Checking increases the likelihood of detecting burst errors. As we have shown in Fig. 3.2.4 that a 2-D Parity check of n bits can detect a burst error of n bits. A burst error of more than n bits is also detected by 2-D Parity check with a high- probability. There is, however, one pattern of error that remains elusive. If two bits in one

data unit are damaged and two bits in exactly same position in another data unit are also damaged, the 2-D Parity check checker will not detect an error. For example, if two data units: 11001100 and 10101100. If first and second from last bits in each of them is changed, making the data units as 01001110 and 00101110, the error cannot be detected by 2-D Parity check.

3.2.3.3 Checksum

In checksum error detection scheme, the data is divided into k segments each of m bits. In the sender’s end the segments are added using 1’s complement arithmetic to get the sum. The sum is complemented to get the checksum. The checksum segment is sent along with the data segments as shown in Fig. 3.2.5 (a). At the receiver’s end, all received segments are added using 1’s complement arithmetic to get the sum. The sum is complemented. If the result is zero, the received data is accepted; otherwise discarded, as shown in Fig. 3.2.5 (b).

Performance The checksum detects all errors involving an odd number of bits. It also detects most errors involving even number of bits.

Figure 3.2.6 Basic scheme for Cyclic Redundancy Checking

This mathematical operation performed is illustrated in Fig. 3.2.7 by dividing a sample 4- bit number by the coefficient of the generator polynomial x 3 +x+1, which is 1011, using the modulo-2 arithmetic. Modulo-2 arithmetic is a binary addition process without any carry over, which is just the Exclusive-OR operation. Consider the case where k = 1101. Hence we have to divide 1101000 (i.e. k appended by 3 zeros) by 1011, which produces the remainder r = 001, so that the bit frame (k+r) = 1101001 is actually being transmitted through the communication channel. At the receiving end, if the received number, i.e., 1101001 is divided by the same generator polynomial 1011 to get the remainder as 000, it can be assumed that the data is free of errors.

1 1 1 1^ k 1 1 0 1 0 0 0

Figure 3.2.7 Cyclic Redundancy Checks (CRC)

0 0 1 r

The transmitter can generate the CRC by using a feedback shift register circuit. The same circuit can also be used at the receiving end to check whether any error has occurred. All the values can be expressed as polynomials of a dummy variable X. For example, for P =

11001 the corresponding polynomial is X4+X3+1. A polynomial is selected to have at least the following properties:

o It should not be divisible by X. o It should not be divisible by (X+1).

The first condition guarantees that all burst errors of a length equal to the degree of polynomial are detected. The second condition guarantees that all burst errors affecting an odd number of bits are detected.

CRC process can be expressed as XnM(X)/P(X) = Q(X) + R(X) / P(X) Commonly used divisor polynomials are:

• CRC-16 = X16 + X15 + X2 + 1

• CRC-CCITT = X16 + X12 + X5 + 1

• CRC-32 = X32 + X26 + X23 + X22 + X16 + X12 + X11 + X10 + X8 + X7 + X
  • X4 + X2 + 1

Performance CRC is a very effective error detection technique. If the divisor is chosen according to the previously mentioned rules, its performance can be summarized as follows:

• CRC can detect all single-bit errors
• CRC can detect all double-bit errors (three 1’s)
• CRC can detect any odd number of errors (X+1)
• CRC can detect all burst errors of less than the degree of the polynomial.
• CRC detects most of the larger burst errors with a high probability.
• For example CRC-12 detects 99.97% of errors with a length 12 or more.

3.2.4 Error Correcting Codes

The techniques that we have discussed so far can detect errors, but do not correct them. Error Correction can be handled in two ways. o One is when an error is discovered; the receiver can have the sender retransmit the entire data unit. This is known as backward error correction. o In the other, receiver can use an error-correcting code, which automatically corrects certain errors. This is known as forward error correction.

In theory it is possible to correct any number of errors atomically. Error-correcting codes are more sophisticated than error detecting codes and require more redundant bits. The number of bits required to correct multiple-bit or burst error is so high that in most of the

Basic approach for error detection by using Hamming code is as follows:

• To each group of m information bits k parity bits are added to form (m+k) bit code as shown in Fig. 3.2.8.
• Location of each of the (m+k) digits is assigned a decimal value.
• The k parity bits are placed in positions 1, 2, …, 2k-1 positions.–K parity checks are performed on selected digits of each codeword.
• At the receiving end the parity bits are recalculated. The decimal value of the k parity bits provides the bit-position in error, if any.

Figure 3.2.9 Use of Hamming code for error correction for a 4-bit data

Figure 3.2.9 shows how hamming code is used for correction for 4-bit numbers (d 4 d 3 d2 d1 ) with the help of three redundant bits (r 3 r 2 r 1 ). For the example data 1010, first r 1 (0) is calculated considering the parity of the bit positions, 1, 3, 5 and 7. Then the parity bits r 2 is calculated considering bit positions 2, 3, 6 and 7. Finally, the parity bits r 4 is calculated considering bit positions 4, 5, 6 and 7 as shown. If any corruption occurs in any of the transmitted code 1010010, the bit position in error can be found out by calculating r 3 r 2 r (^1) at the receiving end. For example, if the received code word is 1110010, the recalculated value of r 3 r 2 r 1 is 110, which indicates that bit position in error is 6, the decimal value of

Example:

Let us consider an example for 5-bit data. Here 4 parity bits are required. Assume that during transmission bit 5 has been changed from 1 to 0 as shown in Fig. 3.2.11. The receiver receives the code word and recalculates the four new parity bits using the same set of bits used by the sender plus the relevant parity (r) bit for each set (as shown in Fig. 3.2.11). Then it assembles the new parity values into a binary number in order of r positions (r8, r4, r2, r1).

Calculations:

Parity recalculated (r8, r4, r2, r1) = 01012 = 510.

Hence, bit 5th^ is in error i.e. d5 is in error. So, correct code-word which was transmitted is:

Figure 3.2.11 Use of Hamming code for error correction for a 5-bit data

Data to be send (^) Data to be send along with redundant bits

Data Received (^) Data Received Minus Parity Bits

Parity bits recalculated

4. What are the different types of errors detected by parity check? Ans: If one bit (or odd number of bits) gets inverted during transmission, then parity check will detect an error. In other words, only odd numbers of errors are detected by parity check. But, if two (or even number) of bits get inverted, and then the error remains undetected.

**5. Draw the LFSR circuit to compute a 4 bit CRC with the polynomial X^4 + X^

• 1? Ans:**

6. Obtain the 4-bit CRC code word for the data bit sequence 10011011100 (leftmost bit is the least significant) using the generator polynomial given in the previous problem. Ans: Divide (Mod-2) 001110110010000 by 10101 to get 4-bit code word: 1101. Details of the steps is given below

001110110010000 10101

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10001 10101

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10000 10101

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10110 10101

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11000 10101

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Ex-OR^ Ex-OR F/F F/F F/F F/F