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UNIT II
The IA-32 Pentium Example: Registers and Addressing, IA-32 Instructions, IA-32 Assembly Language, Program Flow Control, Logic and Shift/Rotate Instructions, I/O Operations, Subroutines, Other Instructions, Program Examples.
2 Marks
1. Write about IA-32.
The Intel architecture (IA) processors operate with 32-bit memory address and 32-bit data operands. They are referred to as IA-32 processors, and the most recent Pentium series.
The first IA-32 processor was 80386 then 80486, Pentium, Pentium Pro, Pentium II, Pentium III, Pentium 4 has been implemented. Theses processors has increasing level of performance, achieved through a number of architectural and microelectronic technology improvements. The latest members of the family have specialized instructions for handling multimedia information and for vector data processing.
2. List out the various register of IA- 32 Register structure ^ ^ General purpose registers
^ ^ floating point registers
^ segment registers ^ instruction pointer (^) status registers
3. Write about General purpose registers
The above diagram shows the general purpose registers. The eight 32-bit registers labeled R0 through R7 are general purpose registers that can be used to bold either data operands or addressing information.
4. Write about floating point registers
There are eight floating point registers for holding double word or quad word (64 bits) floating point data operands. The floating point registers have an extension field to provide a total length of 80 bits, the extra bits are used for increased accuracy while floating point numbers are operated on in the processor.
5. What is Segment registers
There are six segment registers that hold 16-bit segment selectors. A segment selector is a special pointer that identifies a segment in memory. The six segment registers are: ^ ^ CS: code segment register
^ ^ SS: stack segment register
^ DS, ES, FS, GS: data segment registers Code segment (CS) The code segment holds the instructions of a program.
Stack segment (SS) The stack segment contains the processor stack.
Data segment (DS, RD, FS, and GS)
Four data segments are provided for holding data operands. These four data segment registers provide programs with flexible and efficient ways to access data.
The six segment registers below contain selector values that are used in locating these segments in the memory address space.
6. Define Instruction pointer
The EIP register is the 32-bit instruction pointer. The EIP register (or instruction pointer) can also be called "program counter." It contains the offset in the current code segment for the next instruction to be executed. It is advanced from one instruction boundary to the next in straight-line code or it is moved ahead or backwards by a number of instructions when executing JMP,CALL, RET instructions.
Instruction format: Opcode Register Value Example:
MOV EAX, 25
The above instruction moves the decimal value 25 into the EAX register. A number given in this form using the digits 0 through 9 is assumed to be in decimal notation .the suffix B and H are used to specify binary and hexadecimal numbers, respectively .For example the instruction, MOV EAX, 3FAOOH Moves the hex number 3FA00 into EAX.
13. What is direct mode? Give example The memory address of the operand is given by a 32-bit value in the instruction Instruction format: Opcode Register Location Example: MOV EAX, LOCATION The above instruction uses the direct addressing mode to move the doubleword at the memory location specified by the address label LOCATION into register EAX.This assumes that the LOCATION has been defined as an address label for a memory location in the data declaration. If LOCATION represents the address 1000 then this instruction moves the doubleword at 1000 into EAX. In the IA-32 assembly language square brackets can be used to explicitly indicate the direct addressing mode as in the instruction.
MOV EAX, [LOCATION]
14. What is Register mode? Give example The operand is contained in one of the general purpose register specified in the instruction. Instruction format: Opcode Dest.Register Src.Register Example: MOV EAX, ECX Both operands use register mode. The contents of register ECX are copied to register EAX.
Before execution of the above instruction, the contents of ECX and EAX are: ECX 50
EAX
After execution ECX 50
EAX
15. What is Register indirect mode? Give example
The memory address of the operand is contained in one of the eight general purpose register specified in the instruction. Instruction format: Opcode Register [Register] Example: MOV EAX,[EBX] The above instruction moves the contents of LOCATION specified by the register EBX into the register EAX. Before execution of the above instruction, the contents of EAX and EBX are: EAX 00
EBX
After execution EAX 20
EBX
16. What is Base with displacement mode? Give example
An 8-bit or 32-bit signed displacement and one of the eight general purpose register to be used as a base register are specified in the instruction. The effective address of the operand in the sum of the contents of the base register and the displacement.
Instruction format: Opcode Dest.Register [Register]+Displacement Example: MOV EAX, [EBP + 60]
An effective address is computed by: Offset = Base + (Index * Scale) + displacement Instruction format: Opcode Dest.Register [Register1] + [Register2] * Scale factor + Displacement
Example: MOV EAX, [EBP+ESI4 + 200]* The contents of registers ESI is multiplied with the scale factor 4 and then the content of EBP and displacement are added to form an effective address. The contents of memory at the effective address are copied into register EAX
20.Write about IA-32 Instruction
The instructions are variable in length ,ranging from one byte to 12 bytes ,consisting of up to four fields .the OP-code field consists of one or two bytes, with most instructions requiring only one byte, the addressing mode information is contained in one or two bytes immediately following the OP code. For instructions that involve the use of only one register in generating the effective address of an operand ,only one byte is needed in the addressing mode field. Two bytes are needed for encoding the last two addressing modes. These modes use two registers to generate the effective address of a memory operand.
21. What is One byte instruction? Registers can be incremented or decremented by instructions, that occupy one byte. Examples are INC EDI And
DEC ECX In which the general purpose register EDI and ECX are specified by 3-bit codes in the single OP-code byte.
22. What is immediate mode encoding?
The OP-code specifies when the immediate addressing mode is used. For example the instruction MOV EAX, 820
Is encoded into 5 bytes .a one – byte OP code specifies the move operation, the fact that a 32-bit immediate operand is used and the name of the destination register. The OP code byte is directly followed by the 4-byte immediate value of 820.when an 8-bit immediate operand is used, as in the instruction MOV DL, 5 Only two bytes are needed to encode the instruction
23. In which situation a program flow control changes.
There are two main ways in which the flow of executing instructions varies from straight – line sequencing, calls to subroutines and returns from them break straight line sequencing. Also, branch instructions, either conditional or unconditional, can cause a break. The branch instructions are called jumps.
24. Write about Conditional jump instruction
The conditional Jump instructions test the four condition code flags in the status register. The instruction JG LABEL
is an example of a conditional Jump instruction. The condition is greater-than as indicated by the G suffix in the OP code.
25. Write about Unconditional Jump Instruction.(nov 204)
An unconditional Jump instruction, JMP, causes a branch to the instruction at the target address. In addition to using short (one-byte) or long (four-byte) relative signed offsets to determine the target address, as is done in conditional Jump instructions, the JMP instruction also allows the use of other addressing modes.
26. What is the use of Compare Instructions?
It is often necessary to make conditional jumps in a program based on the results of comparing two numbers. The compare instruction CMP dst,src performs the operation
and sets the condition code flags based on the result obtained. Neither of the operands is changed .the first operand is always compared to the second. For example, the compare instruction by a conditional jump that is based on the “greater than” condition, then the jump will take to the target address if the destination operand is greater than the source operand.
27. What is Logical Shift instruction?
An operand can be shifted right or left, using either logical or arithmetic shifts,by a number of bit positions determined by a specified count. The format of the shift instruction is OPcode dst , count Where the destination operand to be shifted is specified by the general addressing modes and the count is given either as an 8-bit immediate value or is contained in the 8-bit register CL.
32. What is SAL and SAR instruction SAL: The operation of SAL is identical to SHL. SAR: SAR (shift arithmetic right) performs a right arithmetic shift on the destination operand. For example, **SAR R0,#
- List out the various rotate instruction** In addition to the shift instructions, there are also four rotate instructions: ^ ^ ROL (Rotate left without the carry flag CF)
^ ^ ROR (Rotate right without the carry flag CF) ^ RCL (Rotate left including the carry flag CF) (^) RCR (Rotate right including the carry flag CF)
34. What is ROL instruction? ^ ^ ROL (rotate) shifts each bit to the left
^ ^ The highest bit is copied into both the Carry flag and into the lowest bit ^ No bits are lost (^) For example , ROL R0,#2
35. What is ROR Instruction? ^ ^ ROR (rotate right) shifts each bit to the right
^ ^ The lowest bit is copied into both the Carry flag and into the highest bit ^ No bits are lost (^) For example , ROR R0,#2
36. What is RCL instruction? ^ ^ RCL (rotate carry left) shifts each bit to the left
^ ^ Copies the Carry flag to the least significant bit ^ Copies the most significant bit to the Carry flag (^) For example , RCL R0,#2
37. What is RCR instruction? ^ ^ RCR (rotate carry right) shifts each bit to the right
^ ^ Copies the Carry flag to the most significant bit ^ Copies the least significant bit to the Carry flag (^) For example , ROR R0,#2
38. What is memory mapped I/O? (^) Instead of having special methods for accessing the values to be read or written, just get them from memory or put them into memory. (^) The device is connected directly to certain main memory locations. 39. Why use memory mapped I/O? ^ ^ Makes programming simpler. (^) Do not have special commands to access I/O devices. o Just use lw and sw. ^ ^ Takes some memory locations o Very few compared to the size of main memory. 40. What is Isolated I/O?
The IA-32 instructions set also have two instructions, with OP codes IN and OUT, that are used only for I/O purposes. The addresses issued by these instructions are in an address space that is separate from the memory address space used by the other instructions. This arrangement is called isolated I/O.
41. Write short notes on block transfers
The IA-32 architecture also has two block transfer I/O instructions REPINS and REPOUTS .they transfer a block lf data serially, one item at a time, between the memory and an I/O device. The S suffix in the
which implicitly uses the EAX register as the multiplicand. The multiplier specified by src can be in a register or in the memory. The full 64-bit product is placed in registers EDX (high-order half) and EAX (low-order half).
46. Write about Division instruction:
The integer divide instruction, IDIV, operates on a 64-bit dividend and a 32-bit divisor to generate a 32-bit quotient and a 32-bit remainder. The format of the instruction is IDIV src The source operand is the divisor. The 64-bit dividend is formed by the contents of register EDX (high-order half) and register EAX (low-order half). After performing the division, the quotient is placed in EAX and the remainder is placed in EDX.
47. What is MMX instruction?
The IA-32 instruction set has a number of instructions that operate in parallel on such data packed into 64-bit quadwords.(A quadword contains 8 bytes or four 16-bit words).These instructions are called multimedia extension (MMX) instructions.
The operands for MMX instructions can be in the memory, or in the eight floating-point registers. Thus, these registers serve a dual purpose. They can hold either floating-point numbers or MMX operands. When used by MMX instructions, the registers are referred to as MM0 through MM7.
48. Write about Vector (SIMD) Floating-Point Operations
A set of instructions that are used to perform arithmetic operations on small group of floating point numbers is provided.SIMD (single-instruction-multiple-data) instructions are useful for vector and matrix calculations in scientific applications.
In Intel terminology, these instructions are called streaming SIMD extension (SSE) instructions. They handle packed 128-bit double quadwords, each consisting of four 32-bit floating-point numbers. Eight additional 128-bit registers, XMM0 to XMM7, are available for holding these operands.
IA-32 REGISTERS
IA- 32 Register structure contains the following
General purpose registers
^ ^ floating point registers
^ segment registers
^ instruction pointer (^) status registers
General purpose registers:
The above diagram shows the general purpose registers. The eight 32-bit registers labeled R0 through R7 are general purpose registers that can be used to bold either data operands or addressing information.
Floating point registers:
There are eight floating point registers for holding doubleword or quadword (64 bits) floating point data operands. The floating point registers have an extension field to provide a total length of 80 bits, the extra bits are used for increased accuracy while floating point numbers are operated on in the processor.
Segment registers:
IA-32 architectures are based on a memory model that associates different areas of the memory, called segments, with different usages. There are three segments, Code segment (CS) The code segment holds the instructions of a program. Stack segment (SS) The stack segment contains the processor stack
Data segment (DS,RD,FS,GS)
The eight general purpose registers are grouped into 3 different types
- Data register
- Pointer register
- Index register
The data register used for holding operands ,and the pointer and index registers for holding address and address indices used to determine the effective address of a memory operand.
The above figure shows the compatibility of the IA-32 register structure with earlier Intel processor register structures.
The Intel’s original 8-bit processors, the data registers were called A,B,C and D.In Intel 16-bit processors, these registers were labeled AX,BX,CX and DX .the high and low-order bytes in each register are identified by suffixes H and L .For example, the two bytes in register AX are referred to as AH and AL.
In IA-32 processors, the prefix E is used to identify the corresponding “extended “32-bit register :EAX,EBX,ECX and EDX.The E – prefix labeling is also used for the other 32-bit registers shown in the above figure. They are the extended versions of the corresponding 16-bit register used in earlier processors.
The IA-32 processor state can be switched dynamically between 32-bit operation and 16-bit operation during program execution on an instruction by instruction basis by the use of instruction prefix bytes.
EAX register:
This is the general–purpose register used for arithmetic and logical operations. This division is seen also in the EBX, ECX, and EDX registers; the code can reference BX, BH, CX, CL, etc. This register has an implied role in both multiplication and division.
EBX register:
This can be used as a general–purpose register, but was originally designed to be the base register, holding the address of the base of a data structure. The easiest example of such a data structure is a singly dimensioned array.
ECX register:
This can be used as a general–purpose register, but it is often used in its special role as a counter register for loops or bit shifting operations.
EDX register:
This can be used as a general–purpose register. It also plays a special part in executing integer multiplication and division. For multiplication, DX or EDX store the more significant bits of the product. The 16 – bit implementation of multiplication uses AX to hold one of the integers to be multiplied and uses the register pair DX:AX to hold the 32-bit product.
The 32–bit implementation of multiplication uses EAX to hold one of the integers to be multiplied and uses the register pair EDX:EAX to hold the 64-bit product.
The Instruction Pointer(EIP)
The EIP register is the 32-bit instruction pointer.The EIP register (or instruction pointer) can also be called "program counter." It contains the offset in the current code segment for the next instruction to be executed. It is advanced from one instruction boundary to the next in straight-line code or it is moved ahead or backwards by a number of instructions when executing JMP,CALL, RET instructions.
The Index Registers
The ESI and EDI registers are used as source and destination addresses for string and array operations.
The ESI “ Extended Source Index ” and EDI “ Extended Destination Index ” facilitate high–speed memory transfers.
IA-32 ADDRESSING MODES (7 Marks April 2015 )
The IA-32 architecture has a large and flexible set of addressing modes. They are designed to access individual data items or data items that are members of an ordered list begins at a specified memory address. There are also several addressing modes that provide mere flexibility in accessing data operands in the memory. The addressing mode of IA-32 includes:
- Immediate mode
- Direct mode
- Register mode
- Register indirect mode
- Base with displacement mode
- Index with displacement mode
- Base with index mode
- Base with index and displacement mode
Immediate mode The operand is contained in the instruction. It is a signed 8-bit or 32-bit number, with the length being specified by a bit in the OP code of the instruction. Thus bit is 0 for the short version and 1 for the long version. Instruction format: Opcode Register Value Example:
MOV EAX,
The above instruction moves the decimal value 25 into the EAX register. A number given in this form using the digits 0 through 9 is assumed to be in decimal notation .the suffix B and H are used to specify binary and hexadecimal numbers, respectively .For example the instruction, MOV EAX,3FAOOH Moves the hex number 3FA00 into EAX.
Direct mode The memory address of the operand is given by a 32-bit value in the instruction Instruction format: Opcode Register Location Example: MOV EAX,LOCATION The above instruction uses the direct addressing mode to move the doubleword at the memory location specified by the address label LOCATION into register EAX.This assumes that the LOCATION has been defined as an address label for a memory location in the data declaration. If LOCATION represents the address 1000 then this instruction moves the doubleword at 1000 into EAX. In the IA-32 assembly language square brackets can be used to explicitly indicate the direct addressing mode as in the instruction.
MOV EAX,[LOCATION]
Register mode The operand is contained in one of the general purpose register specified in the instruction. Instruction format: Opcode Dest.Register Src.Register Example: MOV EAX, ECX Both operands use register mode. The contents of register ECX is copied to register EAX.
Before execution of the above instruction, the contents of ECX and EAX are: ECX 50
EAX
After execution ECX 50
EAX
Register indirect mode The memory address of the operand is contained in one of the eight general purpose register specified in the instruction. Instruction format: Opcode Register [Register] Example: MOV EAX,[EBX] The above instruction moves the contents of LOCATION specified by the register EBX into the register EAX. Before execution of the above instruction, the contents of EAX and EBX are: EAX 00
EBX
