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Today’s Topics

Recap Lecture 4

Instruction Set Encoding

MIPS Instruction Set

Summary

Recap: Lecture 4

Three pillars of Computer Architecture

Hardware, Software and Instruction Set

Instruction Set

Interface between hardware and software

Taxonomy of Instruction Set:

Stack, Accumulator and General Purpose Register

Types and Size of Operands:

Types: Integer, FP and Character

Size: Half word, word, double word

Classification of operations

Arithmetic, data transfer, control and support

Instruction set Encoding

Essential elements of computer instructions

1. Type of the operation to be performed

– This information is encoded in the “operation

code”, or the op-code , field of the machine

language instruction

– Examples: add, mov etc.

2. Place to find the source operand (s)

Possible locations are: CPU registers, memory

cells, I/O locations, part of the instruction itself

Computer Instructions Encoding

3. Place to store the results Possible locations are: CPU registers, memory cells and I/O locations
4. Place to find the next instruction from
   • Address of the next instruction in sequence (this is the default case)
   • Address of the instruction at the branch target location

Variable length Encoding .. Cont’d

• The decision regarding the length depends upon the

range of addressing modes and degree of

independence between op-code and mode

• For example: immediate addressing requires one or

two address field whereas indexed addressing requires

3 or 4 fields

• The length of Intel 80x86 varies between 1 byte and 17

byte and is generally smaller than RICS architecture

which uses fixed length format

Operation and number of operands Address Specifier # 1 Address Specifier #n Address Field # n Address field # 1

Fixed Length Format

- Always has same number of operands

- Addressing modes (if option exist) is specified

in Op-code

- It generally generates the largest code size

- Fields may be used for different purposes, if

necessary

Typical Examples: Alpha, MIPS, PowerPC, SPARC

Operation code Address field # 1 Address field # 3 Address field # 2

Hybrid Length Taxonomy

Based on number of Address Fields

4-address instructions

Specifies the two source operands, the destination operand and

the address of the next instruction

3-address instructions

Specifies addresses for both operands as well as the result

op code destination source 1 source 2 next address op code destination source 1 source 2

Hybrid Length Taxonomy .. Cont’d 2-address instructions

• Overwrites one operand with the result
• One field serves two purposes 1-address instructions

dedicated CPU register, accumulator, to hold one operand and the

result – the address of other operand is specified

op code destination source 1 source 2 op code source 2

Example Evaluate the expression: F = (B + C)*D – E using 0- address through 3-address format

0-Address 1-Address 2-Address 3-Address

PUSH B LDA B LOAD F, B ADD F, B, C

PUSH C ADD C ADD F, C MUL F, F, D

ADD MUL D MUL F, D SUB F, F, E

PUSH D SUB E SUB F, E

MUL STA F

PUSH E

SUB

POP F

Number of

Instructions: 8 5 4 3

Another example:

Using different instruction formats, write pseudo-code to evaluate the following

expression: Z = 4(A+B) – 16(C+58) : Your code should not change the source operands

3-Address 2-Address 1-Address 0-Address

ADD x, A, B MUL y, x, 4 ADD r, C, 58 MUL s, r, 16 SUB Z, y, s LOAD y, B MUL y, 4 LOAD s, C ADD s, 58 MUL s, 16 SUB y, s STORE Z, y ; order changed to reduce code size LDA C ADDA 58 MULA 16 STA S LDA A ADDA B MULA 4 SUBA s STA Z

PUSH C

PUSH 58

ADD

PUSH 16

MUL

PUSH A

PUSH B

ADD

PUSH 4

MUL

SUB

POP Z

4-address instruction

Code size = 1+3+3+3+3 = 13 bytes

# of bytes accessed from memory

13 bytes for instruction fetch +

6 bytes for source operand fetch +

3 bytes for storing destination operand

Total = 22 bytes

op code destination source 1 source 2 next address 1 byte 3 bytes 3 bytes 3 bytes 3 bytes

3-address instruction

Code size = 1+3+3+3 = 10 bytes

# of bytes accessed from memory

10 bytes for instruction fetch +

6 bytes for source operand fetch +

3 bytes for storing destination operand

Total = 19 bytes

1 byte 3 bytes 3 bytes 3 bytes op code destination source 1 source 2