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Computer Architecture and
Memory Hierarchy
Introduction to Combinational and Sequential
Circuits
Combinational and sequential circuits are logic circuits that consist of input variables (X), logic gates (computational circuits), and output variables (Z). The key differences between them are:
Combinational Circuits
Produce an output based solely on the current input variables. Do not have any memory elements to store previous input information.
Sequential Circuits
Produce an output based on both the current input variables and the previous input variables. Contain memory elements, such as latches or flip-flops, that can store binary information and define the state of the circuit.
There are two main types of sequential circuits:
Asynchronous Sequential Circuits
Do not use a clock signal, but rather use the pulses of the input signals. Operate faster than synchronous sequential circuits, but are more difficult to design and have uncertain outputs.
Synchronous Sequential Circuits
Use a clock signal and level inputs (or pulsed inputs with restrictions). Output pulses are the same duration as the clock pulse. Slower than asynchronous circuits, but easier to design and more reliable. Used in synchronous counters, flip-flops, and state machines.
Design of Sequential Circuits
The design of a synchronous sequential circuit involves the following steps:
Obtain a state table or state diagram to specify the circuit's behavior. Determine the number of flip-flops required based on the number of states. Choose the appropriate flip-flops.
Derive the combinational logic structure that, together with the flip- flops, produces the desired circuit behavior.
State Table and State Diagram
The state table representation of a sequential circuit consists of three sections:
Present state: Designates the state of the flip-flops before the clock pulse. Next state: Shows the state of the flip-flops after the clock pulse. Output: Lists the values of the output variables during the present state.
The state diagram is a graphical representation of the same information, where states are represented by circles and state transitions are indicated by directed lines (arcs) connecting the circles.
Basic Computer Architecture
The main components in a typical computer system are:
Processor (CPU) Memory Input/Output (I/O) devices Communication channels (buses) connecting the components
Von Neumann Architecture
The Von Neumann architecture, first published by John von Neumann in 1945, consists of the following key components:
Control Unit (CU) Arithmetic and Logic Unit (ALU) Memory Unit Registers Input/Output
This architecture is based on the stored-program concept, where both instruction data and program data are stored in the same memory. It is still widely used in modern computers.
Central Processing Unit (CPU)
The CPU is the electronic circuit responsible for executing the instructions of a computer program. It contains the ALU, CU, and various registers, including:
Memory Address Register (MAR) Memory Data Register (MDR) Accumulator (AC)
Von-Neumann Architecture
Hardware Requirements
In Von-Neumann architecture, there is no separate data and program memory. Instead, a single memory connection is given to the CPU. This requires more hardware since it will be requiring separate data and address bus for each memory. In contrast to the Harvard architecture, this requires less hardware since only a common memory needs to be reached.
Space Requirements
Von-Neumann architecture requires more space compared to Harvard architecture.
Speed of Execution
Speed of execution is faster in Von-Neumann architecture because the processor fetches data and instructions simultaneously. Speed of execution is slower in Harvard architecture since it cannot fetch the data and instructions at the same time.
Space Usage
Von-Neumann architecture results in wastage of space since if the space is left in the data memory then the instructions memory cannot use the space of the data memory and vice-versa. Harvard architecture does not waste space because the space of the data memory can be utilized by the instruction memory and vice-versa.
Controlling
Controlling becomes complex in Von-Neumann architecture since data and instructions are to be fetched simultaneously. Controlling becomes simpler in Harvard architecture since either data or instructions are to be fetched at a time.
Registers
A register is a very fast computer memory, used to store data/ instruction in-execution. A register is a group of flip-flops with each flip-flop capable of storing one bit of information. An n-bit register has a group of n flip-flops and is capable of storing binary information of n-bits. A register consists of a group of flip-flops and gates. The flip-flops hold the binary information and gates control when and how new information is transferred into a register. The symbolic notation used to describe the micro-operation transfers amongst registers is called Register Transfer Language.
The term register transfer means the availability of hardware logic circuits that can perform a stated micro-operation and transfer the result of the operation to the same or another register.
Common Registers
Accumulator : This is the most common register, used to store data taken out from the memory. General Purpose Registers : These are used to store data intermediate results during program execution. Special Purpose Registers : MAR (Memory Address Register) : Holds the address for the memory unit. MBR (Memory Buffer Register) : Stores instruction and data received from the memory and sent from the memory. PC (Program Counter) : Points to the next instruction to be executed. IR (Instruction Register) : Holds the instruction to be executed.
Key Points
8085 and 8086 are the Intel microprocessor chips. 8085 has an 8-bit data bus and 16-bit memory bus, while 8086 has a 16- bit data bus and 20-bit address bus. 8085 is an accumulator-based microprocessor, where the results of ALU operations are stored in the accumulator. Flags indicate the result of arithmetic and logical operations, which can be used for decision-making processes. Carry Flag : Indicates if the last operation generated a carry. Zero Flag : Indicates if the result of the last operation is zero. Sign Flag : Indicates if the most significant bit (MSB) of the result is 1 (negative). Parity Flag : Indicates if the result of the last operation has an even number of 1's (even parity). Auxiliary Carry Flag : Indicates if the last operation generated a carry from the lower half-word (lower nibble).
RISC and CISC
RISC Processor
RISC stands for Reduced Instruction Set Computer. It has a limited number of instructions, which can be executed very fast because the instructions are small and simple. RISC chips require fewer transistors, making them cheaper to design and produce. The instruction set contains simple and basic instructions, from which more complex instructions can be produced. Most instructions complete in one cycle, allowing the processor to handle many instructions at the same time.
The 2's complement representation is the most suitable and is used in modern computers.
Representation of Characters in Main Memory
Characters can be letters of the alphabet, decimal digits, punctuation marks, etc. They are represented by codes that are usually 6-8 bits long. A 32-bit word can store 4 characters in ASCII format.
Representation of Instructions in Main Memory
A main memory word can be used to represent an instruction. One part of the word specifies the operation to be performed, and the other part specifies the operand address. The different ways in which operands can be named in machine instructions are called addressing modes.
Big-Endian and Little-Endian Assignments
To enable instructions to refer to individual bytes, the smallest addressable unit in most computers is a byte rather than a word, and such computers are called byte-addressable. In Big-Endian assignment, bytes are numbered starting with the most significant byte of a word, and the word is given the same address as its most significant byte. In Little-Endian assignment, bytes are numbered from the least significant byte of a word, and the word is given the address of its least significant byte. Both assignments are used in commercial machines, and byte addresses 0, 4, 8, etc. are taken as the addresses of successive words in the memory.
Main Memory Operations
To execute an instruction, the instruction must be transferred from the main memory to the CPU. Operands and results must also be moved between the main memory and the CPU. The two basic operations involving the main memory are: Load (or Fetch or Read): Transfers a copy of the contents of a specific memory location to the CPU, while the word in the main memory remains unchanged. Store (or Write): Transfers a word of information from the CPU to a specific main memory location, destroying the former contents of that location.
Instructions and Instruction Sequencing
A computer must have instructions capable of performing four types of operations:
Data transfers between the main memory and the CPU registers Arithmetic and logic operations on data Program sequencing and control I/O transfers Notations used: Register Transfer Notation (RTN): Identifies the names for the addresses of memory locations and CPU registers. Assembly Language Notation: Represents the same operations in assembly language format.
Basic Instruction Types
Three-address instruction: Represents a high-level instruction, such as C = A + B, which requires fetching the contents of memory locations A and B, performing the addition, and storing the result in memory location C. The same action is performed by a single machine instruction (three- address instruction) in the form: Add A, B, C. Operands A and B are called the source operands, C is called the destination operand, and Add is the operation to be performed on the operands.
Instruction Formats
General Format
The general format of an instruction is as follows:
Operation Source1, Source2, Destination
If k bits are needed to specify the memory address of each operand, the encoded form of the above instruction must contain 3k bits for addressing purposes + the bits needed to denote the operation.
Two-Address Instruction
An alternative method is to use a two-address instruction of the form:
Operation Source, Destination
For example, the instruction Add A, B performs the operation:
B ← [B]
Here, the sum is calculated and the result is stored in location B, replacing the original contents of this location. The operand B acts as both source and destination.
In the case of a three-address instruction, the contents of A and B were not destroyed. However, in the two-address instruction, the contents of B are destroyed. This problem can be solved by using another two-address
However, there is one problem with sign magnitude, and that is we have two representations of 0: * +0 = 000000 * -0 = 100000
2's Complement
To represent a negative number in this form, first we need to take the 1's complement of the number represented in simple positive binary form, and then add 1 to it. For example: * (-8)10 = (1000)2 * 1's complement of 1000 = 0111 * Adding 1 to it, 0111 + 1 = 1000
The range of numbers represented by 2's complement is (-2^(n-1)) to (2^(n-1) - 1).
Floating Point Representation of Numbers
32-bit Representation (IEEE Standard)
Normalization
Floating point numbers are usually normalized, where the exponent is adjusted so that the leading bit (MSB) of the mantissa is 1. Since this bit is always 1, there is no need to store it.
For example, we represent 3.625 in 32-bit format: * 3.625 = 11.101 × 2^0 * On normalizing, 11.101 × 2^0 = 1.1101 × 2^1 * On biasing the exponent = 127 + 1 = 128 = (10000000)2 * The significand (mantissa) is 11010000000000000000000
The final 32-bit representation is: * Sign bit = 0 (positive number) * Exponent = 10000000 * Significand = 11010000000000000000000
64-bit Representation (IEEE Standard)
The procedure for 64-bit representation is similar to the 32-bit case. For example, we represent -3.625 in 64-bit format: * 3.625 = 11.101 × 2^0 * On normalizing, 11.101 × 2^0 = 1.1101 × 2^1 * The exponent field is 01000000000 = 512 * The significand field is 1101000000000000000000000000000000000000000000000000 (52 bits) * The sign bit is set to 1 (negative number)
Floating Point Addition and Subtraction
Floating Point Addition
To add two floating point numbers, we follow these steps: 1. Normalize the result. 2. Align the exponents by shifting the mantissa of the number with the smaller exponent. 3. Add the mantissas. 4. Normalize the result.
For example, let's add 9.75 and 0.5625 in 32-bit floating point representation: * 9.75's representation = 0 10000010
00111000000000000000000 * 0.5625's representation = 0 01111110 00100000000000000000000 * Shift the mantissa of 0.5625 right by 4 bits to align the exponents. * Add the mantissas: 0.00010010000000000000000 + 1.00111000000000000000000 = 1.01001010000000000000000 * The final 32-bit representation of the result is 0 10000010
Floating Point Subtraction
Subtraction is similar to addition, with the following differences: 1. We subtract the mantissas instead of adding them. 2. The sign bit of the result is the sign of the greater number.
For example, let's subtract -0.5625 from 9.75 in 32-bit floating point representation: * 9.75's representation = 0 10000010 00111000000000000000000 * -0.5625's representation = 1 01111110 00100000000000000000000 * Shift the mantissa of -0.5625 right by 4 bits to align the exponents. * Subtract the mantissas: 1.00111000000000000000000 - 0.00010010000000000000000 = 1.00100110000000000000000 * The final 32-bit representation of the result is 0 10000010 00100110000000000000000.
Microprocessor Instruction Cycle
The instruction cycle, also known as the fetch-decode-execute cycle, is the basic operational process of a microprocessor. It can be divided into three distinct phases:
Fetch Phase
In this phase, the program counter's value is used to access a specific cell from the program memory, which contains the instruction to be executed. This instruction is then placed into the instruction register (IR).
Decode Phase
In this phase, the control unit of the CPU decodes the instruction in the IR: - It determines the type of instruction (e.g. data processing, memory access, etc.) by decoding the opcode. - It fetches the operands required for the instruction from the appropriate locations (registers, memory, etc.).
Execute Phase
In this phase, the actual operation specified by the instruction is performed. If it is a data processing instruction, the operands are passed through the ALU and/or other data manipulation units for processing. The result is then stored in either a CPU register or the data memory, depending on the architecture and the instruction.
The instruction cycle then repeats for the next instruction.
Carry flag are added to the contents of the accumulator, and the result is stored in the accumulator. Example: ADC K | | ADI | 8-bit data | Add the immediate to the accumulator | The 8-bit data is added to the contents of the accumulator, and the result is stored in the accumulator. Example: ADI 55H | | ACI | 8-bit data | Add the immediate to the accumulator with carry | The 8- bit data and the Carry flag are added to the contents of the accumulator, and the result is stored in the accumulator. Example: ACI 55H | | LXI | Reg. pair, 16-bit data | Load the register pair immediate | The instruction stores 16-bit data into the register pair designated in the operand. Example: LXI K, 3025H | | DAD | Reg. pair | Add the register pair to H and L registers | The 16-bit data of the specified register pair are added to the contents of the HL register. Example: DAD K | | SUB | R, M | Subtract the register or the memory from the accumulator | The contents of the register or the memory are subtracted from the contents of the accumulator, and the result is stored in the accumulator. Example: SUB K | | SBB | R, M | Subtract the source and borrow from the accumulator | The contents of the register or the memory and the Borrow flag are subtracted from the contents of the accumulator, and the result is placed in the accumulator. Example: SBB K | | SUI | 8-bit data | Subtract the immediate from the accumulator | The 8-bit data is subtracted from the contents of the accumulator, and the result is stored in the accumulator. Example: SUI 55H | | SBI | 8-bit data | Subtract the immediate from the accumulator with borrow | The contents of register H are exchanged with the contents of register D, and the contents of register L are exchanged with the contents of register E. Example: XCHG | | INR | R, M | Increment the register or the memory by 1 | The contents of the designated register or the memory are incremented by 1, and the result is stored at the same place. Example: INR K | | INX | R | Increment register pair by 1 | The contents of the designated register pair are incremented by 1, and the result is stored at the same place. Example: INX K | | DCR | R, M | Decrement the register or the memory by 1 | The contents of the designated register or memory are decremented by 1, and the result is stored at the same place. Example: DCR K | | DCX | R | Decrement the register pair by 1 | The contents of the designated register pair are decremented by 1, and the result is stored at the same place. Example: DCX K | | DAA | None | Decimal adjust accumulator | The contents of the accumulator are changed from a binary value to two 4-bit BCD digits. If the value of the low-order 4-bits in the accumulator is greater than 9 or if AC flag is set, the instruction adds 6 to the low-order four bits. If the value of the high-order 4-bits in the accumulator is greater than 9 or if the Carry flag is set, the instruction adds 6 to the high-order four bits. Example: DAA |
Logical Instructions in 8085
| Opcode | Operand | Meaning | Explanation | | --- | --- | --- | --- | | CMP | R, M | Compare the register or memory with the accumulator | The contents of the operand (register or memory) are compared with the contents of the accumulator. | | CPI | 8-bit data | Compare immediate with the accumulator | The second byte data is compared with the contents of the accumulator. | | ANA | R, M | Logical AND register or memory with the accumulator | The contents of the accumulator are logically AND with the contents of the register or memory, and the result is placed in the accumulator. | | ANI | 8-
bit data | Logical AND immediate with the accumulator | The contents of the accumulator are logically AND with the 8-bit data, and the result is placed in the accumulator. | | XRA | R, M | Exclusive OR register or memory with the accumulator | The contents of the accumulator are Exclusive OR with the contents of the register or memory, and the result is placed in the accumulator. | | XRI | 8-bit data | Exclusive OR immediate with the accumulator | The contents of the accumulator are Exclusive OR with the 8- bit data, and the result is placed in the accumulator. | | ORA | R, M | Logical OR register or memory with the accumulator | The contents of the accumulator are logically OR with the contents of the register or memory, and the result is placed in the accumulator. | | ORI | 8-bit data | Logical OR immediate with the accumulator | The contents of the accumulator are logically OR with the 8-bit data, and the result is placed in the accumulator. | | RLC | None | Rotate the accumulator left | Each binary bit of the accumulator is rotated left by one position. Bit D7 is placed in the position of D0 as well as in the Carry flag. CY is modified according to bit D7. | | RRC | None | Rotate the accumulator right | Each binary bit of the accumulator is rotated right by one position. Bit D0 is placed in the position of D7 as well as in the Carry flag. CY is modified according to bit D0. | | RAL | None | Rotate the accumulator left through carry | Each binary bit of the accumulator is rotated left by one position through the Carry flag. Bit D7 is placed in the Carry flag, and the Carry flag is placed in the least significant position D0. CY is modified according to bit D7. | | RAR | None | Rotate the accumulator right through carry | Each binary bit of the accumulator is rotated right by one position through the Carry flag. Bit D0 is placed in the Carry flag, and the Carry flag is placed in the most significant position D7. CY is modified according to bit D0. | | CMA | None | Complement accumulator | The contents of the accumulator are complemented. | | CMC | None | Complement carry | The Carry flag is complemented. No other flags are affected. | | STC | None | Set Carry | Set Carry |
Other Instructions in 8085
Data Transfer Instructions
MOV, MVI, PUSH, POP, IN, OUT, LDA, STA, LXI, LDAX, STAX, LHLD, SHLD, XCHG
Branching and Jumping Instructions
JC, JNC, JZ, JNZ, JP, JM, JPE, JPO
CC, CNC, CZ, CNZ, CP, CM, CPE, CPO
RC, RNC, RZ, RNZ, RP, RM, RPE, RPO
Control Instructions
| Opcode | Operand | Meaning | Explanation | | --- | --- | --- | --- | | NOP | None | No operation | No operation is performed, i.e., the instruction is fetched and decoded. The CPU finishes executing the current instruction and stops further execution. An interrupt or reset is necessary to exit from the halt state. | | DI | None | Disable interrupts | The interrupt enable flip-flop is
LHLD address (load contents of 16-bit memory location into H-L register pair) IN 35H (read the data from port whose address is 35H)
4. Register Indirect Addressing Mode
The data to be operated is available inside a memory location, and that memory location is indirectly specified by a register pair. Examples: MOV A, M (move the contents of the memory location pointed by the H- L pair to the accumulator) LDAX B (move contents of B-C register to the accumulator) LXI H, 9570H (load immediate the H-L pair with the address of the location 9570H)
5. Implied/Implicit Addressing Mode
The operand is hidden, and the data to be operated is available in the instruction itself. Examples: CMA (finds and stores the 1's complement of the contents of accumulator A in A) RLC (rotate accumulator A left by one bit)
More Insights on Addressing
Direct Addressing Mode
The effective address of the operand is present in the instruction itself. There is a single memory reference to access the data. No additional calculations are required to find the effective address of the operand. Examples: LDA 9500H (A ← [9500]) IN 80H (A ← [80])
Indirect Addressing Mode
The address field of the instruction gives the address where the effective address is stored in memory. This slows down the execution, as it includes multiple memory lookups to find the operand.
Memory Organization in Computer
Architecture
Memory Unit
A memory unit is the collection of storage units or devices together.
Types of Memory
There are two main types of memory in a computer system:
Primary Memory : This is the main memory of the computer system, which is directly accessible by the CPU. It includes: RAM (Random Access Memory) : Volatile memory that can be read from and written to by the CPU.
ROM (Read-Only Memory) : Non-volatile memory that can only be read by the CPU.
Secondary Memory : This is the auxiliary memory of the computer system, which is not directly accessible by the CPU. It includes:
Magnetic Disks : Hard Disk Drives (HDDs) and Solid-State Drives (SSDs). Optical Disks : CD-ROMs, DVDs, and Blu-ray Discs. Magnetic Tapes : Used for backup and archival storage.
Memory Hierarchy
The memory hierarchy in a computer system is organized based on the speed and capacity of the memory devices. The hierarchy is as follows:
Registers : Fastest memory, located inside the CPU. Cache Memory : Faster than main memory, located close to the CPU. Main Memory (RAM) : Slower than cache, but faster than secondary memory. Secondary Memory (Disks) : Slower than main memory, but has much larger capacity.
The closer the memory is to the CPU, the faster it is, but the smaller its capacity. The farther the memory is from the CPU, the slower it is, but the larger its capacity.
Memory Addressing
Memory addressing is the process of uniquely identifying a memory location using a memory address. The size of the memory address determines the maximum addressable memory space.
For example, in an 8-bit microprocessor, the memory address is 8 bits wide, allowing a maximum of 2^8 = 256 unique memory locations to be addressed.
Memory Mapping
Memory mapping is the process of assigning physical memory locations to logical memory addresses. This allows the CPU to access memory locations using logical addresses, which are then translated to physical addresses.
Transparent Mode : The DMA controller transfers data only when the CPU is not using the bus.
The 8237 DMA controller is a widely used DMA controller in computer systems.
Memory Unit and Memory Hierarchy
Memory Unit
The memory unit stores binary information in the form of bits. Memory/ storage is classified into two categories:
Volatile Memory : This loses its data when power is switched off. Non-Volatile Memory : This is a permanent storage and does not lose any data when power is switched off.
Memory Hierarchy
The total memory capacity of a computer can be visualized by a hierarchy of components. The memory hierarchy system consists of all storage devices contained in a computer system, from the slow Auxiliary Memory to the fast Main Memory and Cache memory.
Auxiliary memory access time is generally 1000 times that of the main memory, hence it is at the bottom of the hierarchy. The main memory occupies the central position because it is equipped to communicate directly with the CPU and with auxiliary memory devices through the Input/Output processor (I/O). When a program not residing in main memory is needed by the CPU, it is brought in from auxiliary memory. Programs not currently needed in main memory are transferred into auxiliary memory to provide space in main memory for other programs that are currently in use. The cache memory is used to store program data which is currently being executed in the CPU. The approximate access time ratio between cache memory and main memory is about 1 to 7~10.
Memory Access Methods
To access data from any memory, it must first be located, and then the data is read from the memory location. The following are the methods to access information from memory locations:
Random Access : Main memories are random access memories, in which each memory location has a unique address. Using this unique address, any memory location can be reached in the same amount of time in any order. Sequential Access : This method allows memory access in a sequence or in order.
Direct Access : In this mode, information is stored in tracks, with each track having a separate read/write head.
Main Memory
The memory unit that communicates directly within the CPU, Auxiliary memory, and Cache memory is called the main memory. It is the central storage unit of the computer system. It is a large and fast memory used to store data during computer operations. Main memory is made up of RAM and ROM, with RAM integrated circuit chips holding the major share.
RAM (Random Access Memory)
DRAM (Dynamic RAM) : Made of capacitors and transistors, and must be refreshed every 10~100 ms. SRAM (Static RAM) : Has a six-transistor circuit in each cell and retains data until powered off. NVRAM (Non-Volatile RAM) : Retains its data even when turned off. Example: Flash memory.
ROM (Read-Only Memory)
ROM is non-volatile and is more like a permanent storage for information. It also stores the bootstrap loader program to load and start the operating system when the computer is turned on. PROM (Programmable ROM), EPROM (Erasable PROM), and EEPROM (Electrically Erasable PROM) are some commonly used ROMs.
Auxiliary Memory
Devices that provide backup storage are called auxiliary memory. For example, magnetic disks and tapes are commonly used auxiliary devices. Other devices used as auxiliary memory are magnetic drums, magnetic bubble memory, and optical disks. Auxiliary memory is not directly accessible to the CPU and is accessed using the Input/Output channels.
Cache Memory
The data or contents of the main memory that are used again and again by the CPU are stored in the cache memory so that they can be easily accessed in a shorter time. Whenever the CPU needs to access memory, it first checks the cache memory. If the data is not found in the cache memory, the CPU moves on to the main memory. It also transfers blocks of recent data into the cache and keeps deleting the old data to accommodate the new one.
Hit Ratio
The performance of cache memory is measured in terms of a quantity called the hit ratio. When the CPU refers to memory and finds the word in the
