Computer Architecture: Main Memory (Part I), Summaries of Architecture

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Computer Architecture:

Main Memory (Part I)

Prof. Onur Mutlu

Carnegie Mellon University

(reorganized by Seth)

Main Memory

Ideal Memory 

Zero access time (latency)

Infinite capacity

Zero cost

Infinite bandwidth (to support multiple accesses in parallel)

The Problem 

Ideal memory’s requirements oppose each other

Bigger is slower 

Bigger

Takes longer to determine the location

Faster is more expensive 

Memory technology: SRAM vs. DRAM

Higher bandwidth is more expensive 

Need more banks, more ports, higher frequency, or fastertechnology

Static random access memory

Two cross coupled inverters store a single bit 

Feedback path enables the stored value to persist in the “cell”



4 transistors for storage



2 transistors for access

Memory Technology: SRAM

row select

bitline

_bitline

An Aside: Phase Change Memory 

Phase change material (chalcogenide glass) exists in two states:



Amorphous: Low optical reflexivity and high electrical resistivity



Crystalline: High optical reflexivity and low electrical resistivity

PCM is resistive memory: High resistance (0), Low resistance (1)

Lee, Ipek, Mutlu, Burger,

Architecting Phase Change Memory as a Scalable DRAM

Alternative,

ISCA 2009.

Memory Bank Organization and Operation



Read access sequence:1. Decode row address& drive word-lines

2. Selected bits drive bit-lines - Entire row read 3. Amplify row data4. Decode column address & select subsetof row - Send to output 5. Precharge bit-lines - For next access

Why Memory Hierarchy? 

We want both fast and large

But we cannot achieve both with a single level of memory

Idea: Have multiple levels of storage (progressively biggerand slower as the levels are farther from the processor)and ensure most of the data the processor needs is kept inthe fast(er) level(s)

A Modern Memory Hierarchy

Register

File

words,

sub

nsec

L

cache

KB,

~nsec

L

cache

KB

1MB,

many

nsec

L

cache,

Main

memory

(DRAM),

GB,

nsec

Swap

Disk

GB,

msec

manual/compilerregister

spilling

automaticdemand paging

AutomaticHW

cache

management

MemoryAbstraction

The DRAM Subsystem

Page Mode DRAM 

A DRAM bank is a 2D array of cells: rows x columns

A

DRAM row

is also called a

DRAM page

Sense amplifiers

also called

row buffer

Each address is a <row,column> pair

Access to a

closed row



Activate command opens row (placed into row buffer)



Read/write command reads/writes column in the row buffer



Precharge command closes the row and prepares the bank fornext access

Access to an

open row



No need for activate command

DRAM Bank Operation

Row Buffer

(Row 0, Column 0)

Row decoder

Column mux

Row address 0

Column address 0

Data

Row 0Empty

(Row 0, Column 1)

Column address 1

(Row 0, Column 85)

Column address 85

(Row 1, Column 0)

HITHIT

Row address 1

Row 1

Column address 0

CONFLICT!

Columns

Rows

Access Address:

128M x 8-bit DRAM Chip

DRAM Rank and Module 

Rank: Multiple chips operated together to form a wideinterface

All chips comprising a rank are controlled at the same time 

Respond to a single command



Share address and command buses, but provide different data

A DRAM module consists of one or more ranks 

E.g., DIMM (dual inline memory module)



This is what you plug into your motherboard

If we have chips with 8-bit interface, to read 8 bytes in asingle access, use 8 chips in a DIMM