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Compiler Optimizations for Reducing Cache Misses: Techniques and Examples, Slides of Computer Aided Design (CAD)

Baba Ghulam Shah Badhshah University Computer Aided Design (CAD)

Various compiler optimizations to reduce cache misses, including techniques such as reordering procedures, merging arrays, loop interchange, loop fusion, and blocking. Real-life examples are provided to illustrate the benefits of each optimization.

Typology: Slides

2012/2013

Uploaded on 04/24/2013

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Reducing Misses using Compiler

Optimizations

McFarling [1989] reduced caches misses by 75% on 8KB direct

mapped cache, 4 byte blocks in software

Instructions

Reorder procedures in memory so as to reduce conflict misses

Profiling to look at conflicts(using tools they developed)

Data

Merging Arrays: improve spatial locality by single array of compound

elements vs. 2 arrays

Loop Interchange: change nesting of loops to access data in order stored in

memory

Loop Fusion: Combine 2 independent loops that have same looping and

some variables overlap

Blocking: Improve temporal locality by accessing “blocks” of data

repeatedly vs. going down whole columns or rows

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Reducing Misses using Compiler

Optimizations

 McFarling [1989] reduced caches misses by 75% on 8KB direct

mapped cache, 4 byte blocks in software

 Instructions

 Reorder procedures in memory so as to reduce conflict misses

 Profiling to look at conflicts(using tools they developed)

 Data

 Merging Arrays : improve spatial locality by single array of compound

elements vs. 2 arrays

 Loop Interchange : change nesting of loops to access data in order stored in

memory

 Loop Fusion : Combine 2 independent loops that have same looping and

some variables overlap

 Blocking : Improve temporal locality by accessing “blocks” of data

repeatedly vs. going down whole columns or rows

Merging Arrays Example

/* Before: 2 sequential arrays */ int val[SIZE]; int key[SIZE];

/* After: 1 array of stuctures */ struct merge { int val; int key; }; struct merge merged_array[SIZE];

Reducing conflicts between val & key;

improve spatial locality

Loop Fusion Example

/* Before */ for (i = 0; i < N; i = i+1) for (j = 0; j < N; j = j+1) a[i][j] = 1/b[i][j] * c[i][j]; for (i = 0; i < N; i = i+1) for (j = 0; j < N; j = j+1) d[i][j] = a[i][j] + c[i][j];

/* After */ for (i = 0; i < N; i = i+1) for (j = 0; j < N; j = j+1) { a[i][j] = 1/b[i][j] * c[i][j]; d[i][j] = a[i][j] + c[i][j];}

2 misses per access to a & c vs. one miss per access; improve

spatial locality

Blocking Example

/* Before */

for (i = 0; i < N; i = i+1)

for (j = 0; j < N; j = j+1) {r = 0; for (k = 0; k < N; k = k+1){ r = r + y[i][k]*z[k][j];}; x[i][j] = r; };

 Two Inner Loops:

 Read all NxN elements of z[]

 Read N elements of 1 row of y[] repeatedly

 Write N elements of 1 row of x[]

 Capacity Misses a function of N & Cache Size:

 2N^3 + N^2 => (assuming no conflict; otherwise …)

 Idea: compute on BxB submatrix that fits

Reducing Conflict Misses by Blocking

 Conflict misses in caches not FA vs. Blocking size

 Lam et al [1991] a blocking factor of 24 had a fifth the misses vs. 48

despite both fit in cache

Blocking Factor

Miss Rate

Fully Associativ e Cache

Dire ct M appe d Cache

Pe rformance Improv e me nt

compre ss

chole sky (nasa7)

spice

mxm (nasa7)

btrix (nasa7)

tomcatv

gmty (nasa7)

v pe nta (nasa7)

me rge d arrays

loop inte rchange

loop fusion blocking

Compiler Optimizations for Reducing Cache Misses: Techniques and Examples, Slides of Computer Aided Design (CAD)

Related documents

Partial preview of the text

Download Compiler Optimizations for Reducing Cache Misses: Techniques and Examples and more Slides Computer Aided Design (CAD) in PDF only on Docsity!

Reducing Misses using Compiler

Optimizations

 McFarling [1989] reduced caches misses by 75% on 8KB direct

mapped cache, 4 byte blocks in software

 Instructions

 Reorder procedures in memory so as to reduce conflict misses

 Profiling to look at conflicts(using tools they developed)

 Data

 Merging Arrays : improve spatial locality by single array of compound

elements vs. 2 arrays

 Loop Interchange : change nesting of loops to access data in order stored in

memory

 Loop Fusion : Combine 2 independent loops that have same looping and

some variables overlap

 Blocking : Improve temporal locality by accessing “blocks” of data

repeatedly vs. going down whole columns or rows

Merging Arrays Example

Reducing conflicts between val & key;

improve spatial locality

Loop Fusion Example

2 misses per access to a & c vs. one miss per access; improve

spatial locality

Blocking Example

 Two Inner Loops:

 Read all NxN elements of z[]

 Read N elements of 1 row of y[] repeatedly

 Write N elements of 1 row of x[]

 Capacity Misses a function of N & Cache Size:

 2N^3 + N^2 => (assuming no conflict; otherwise …)

 Idea: compute on BxB submatrix that fits

Reducing Conflict Misses by Blocking

 Conflict misses in caches not FA vs. Blocking size

 Lam et al [1991] a blocking factor of 24 had a fifth the misses vs. 48

despite both fit in cache

Summary of Compiler Optimizations to

Reduce Cache Misses (by hand)