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Nirma University Institute of Technology Semester End Examination (RPR), December - 2015 B. Tech. in Computer Engineering, Semester-IV CE402 Computer Organization Roll/ Supervisor’s initial Exam No with date Time : 3 Hours Max Marks: 100 Instructions: i) Attempt all questions. ii) Figures to the right indicate full marks. iii) Draw neat sketches wherever necessary. iv) Assume suitable data wherever necessary and specify them. v) Use section wise separate answer sheets. SECTION - I Q.1. Answer the following: [18] A. The outputs of four registers, RO, Rl, R2 and R3, are connected [03] through 4-to-1 line multiplexers to the inputs of a fifth register, RS. Each register is 8 bits long. The required transfers are dictated by four timing variables TO through TS as follows: To: RS — RO Ti RS RL Ta: RS — R2 Tz: RS — R3 The timing variables are mutually exclusive, which means that only one variable is equal to 1 at any given time, while the other three are equal to 0. Draw a block diagram showing the hardware implementation of the register transfers. B. Represent the following conditional control statements by register [03] transfer statements: If (P=1) then (R1<-R2) else if (Q=1) then (R1<-R1-R2) else RI--R1+R3 Cc. An output program is stored in memory at address A200. It is [03] executed after the computer recognizes an interrupt when FGO becomes a 1 and IEN = 1. What instruction must be placed at address 1? What must be the last two instructions of the output program? D. The register transfer statements for a register Rand the memory [03] in a computer are as follows (the X’s are control functions that occur at random): Page i of 6 
