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Nirma University Institute of Technology Semester End Examination (IR), May - 2015 B. Tech. in Computer Engineering / Information Technology, Semester-IV CE402 Computer Organization Roll/ Supervisor’s initial Exam No with date Time : 3 Hours Max Marks: 100 Instructions: i) Attempt all questions. ii) Figures to the right indicate full marks. iii) Draw neat sketches wherever necessary. iv) Assume suitable data wherever necessary and specify them. v) Use seclion wise separate answer sheets. SECTION - 1 Q.1. Answer the following: [18] A. Design a common bus system using three-state buffers for 4 [03] registers of 2 bits each. B. Show the hardware that implements the following register [03] transfer statements: Qf : Ri —RL—R2 aT:R1<0 {at+a)T:RI<—RI’ C. An output program is stored in memory at address A200. It is [03] executed after the computer recognizes an interrupt when FGO becomes a 1 and IEN = 1. What instruction must be placed at address 1? What must be the last two instructions of the output program? D. Make the following changes to the basic computer. Add a register [03] X1 to the bus system, X1 is selected with S2S1S9 = 000. Replace the ISZ instruction with an instruction that loads the content of a memory word into X1. Add a register reference instruction RISZ: Increment X1 and skip next instruction if zero. Discuss the effect of this change. E. Differentiate between [03] i) microoperation and microinstruction ii) microprogram and microcode F. Consider a computer with four floating point pipeline processors. [03] Suppose that each processor uses a cycle time of 25 ns. How long will it take to perform 600 floating point operations? Is there a difference if the same 600 operations are performed using a Page 1 of 5 
