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A tutorial for the microelectronics devices and circuits fall 2005 course, focusing on upgrading device models, updating the schematic for transient simulation, and performing transient simulation, analysis, and parametric simulation using cadence. The goal is to find the minimum power required to meet specifications for a given load capacitor and maximum required rise and fall times.
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By Kerwin Johnson
Version: 10/24/
(based on 6.776 setup by Mike Perrott)
In this second tutorial we will build on what we learned in the first tutorial. We will learn more sophisticated modeling techniques and more powerful simulation skills. We will use them to answer the question, “For a given load capacitor and a maximum required rise and fall time what is the minimum power required to meet these specs?”
For this we will find useful models that automatically include the increase in source and drain depletion capacitance with increases in the device size. So we will use a parameterized subcircuit around the mos1 model that we created in the first tutorial.
In order to find the rise time, the fall time and the power per cycle we will run a transient simulation.
In order to answer the optimization question, we will use a parametric simulation as an insightful way to pursue the answer.
nmos6012p (d g s b) nmos6012i
ends
inline subckt pmos6012p (d g s b)
parameters w=6e-6 l=1.5e-6 as=2.7e-
model pmos6012i mos
pmos6012p (d g s b) pmos6012i
ends
If you have changed the name of the model file, then you need to change the location in ADE as well.
Courtesy of Cadence Design Systems, Inc. Used with permission.
Courtesy of Cadence Design Systems, Inc. Used with permission.
In this section we will plot the transient outputs, show a quick way to measure time differences in the waveform window and calculate rise time, delay and power consumed.
First we plot.
Courtesy of Cadence Design Systems, Inc. Used with permission.
initial value to 90% of the difference above the initial value. This avoids counting long tails as part of the rise time.
d) The final formula should look like. riseTime(clip(VT("/output"),4.5u,5u),0,nil,5,nil,10,90) e) Add this to your ADE outputs window. Plot it or evaluate the buffer (which will consume the formula, so remember to push it onto the stack) to see the value. f) Do the same for fall time.
c) The expression in the window should be: delay(VT("/input"),2.5,5,"rising",VT("/output"),2.5,5,"falling") d) Add this to your ADE->outputs as falldelay. e) Compute the risedelay and add it to your ADE->outputs.
Courtesy of Cadence Design Systems, Inc. Used with permission.
Courtesy of Cadence Design Systems, Inc. Used with permission.
the red dot on the positive terminal of vdc symbol in the schematic. This will write IT(“/V0/PLUS”) in your calculator, if V0 is the name of your supply. b) Calculate the instantaneous power. The instantaneous power will be the current leaving the supply times the voltage or -IT("/V0/PLUS")VT("/vdd!"). You can plot this if you want. c) Now calculate the average power consumed per period by integrating over one cycle and dividing by the duration. Use SpecialFunction->integ. Start at 4.5u and end at 5.5u. Divide by 1u. The formula in the calculator window will look like: integ(-IT("/V0/PLUS")VT("/vdd!"),4.5u,5.5u)/1u d) Add this to your outputs as avepow.
Courtesy of Cadence Design Systems, Inc. Used with permission.
Waveform.
Courtesy of Cadence Design Systems, Inc. Used with permission.
As you can see parametric analysis can allow you to explore 1, 2, 3 or more dimensional slices through your design space, if you can imagine a way to tie a variable to some portion of the design space.
Courtesy of Cadence Design Systems, Inc. Used with permission.