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Fall 2005 Tutorial: Upgrading Device Models & Transient Simulation in Microelectronics, Study Guides, Projects, Research of Very large scale integration (VLSI)

A tutorial for the microelectronics devices and circuits fall 2005 course, focusing on upgrading device models, updating the schematic for transient simulation, and performing transient simulation, analysis, and parametric simulation using cadence. The goal is to find the minimum power required to meet specifications for a given load capacitor and maximum required rise and fall times.

Typology: Study Guides, Projects, Research

2018/2019

Uploaded on 10/04/2019

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6.012 Microelectronics Devices and Circuits Fall 2005 1
Cadence Tutorial (Part Two)
By Kerwin Johnson
Version: 10/24/05
(based on 6.776 setup by Mike Perrott)
Table of Contents
Introduction.......................................................... .............................2
Upgrade the Device Models...............................................................3
Update the Schematic for the Transient Simulation...........................6
Transient Simulation.........................................................................9
Analysis...........................................................................................11
Plot the Transient Output ............................................................11
Calculate Delays, Rise Times and Power Consumption.................12
Parametric Simulation.....................................................................15
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Download Fall 2005 Tutorial: Upgrading Device Models & Transient Simulation in Microelectronics and more Study Guides, Projects, Research Very large scale integration (VLSI) in PDF only on Docsity!

Cadence Tutorial (Part Two)

By Kerwin Johnson

Version: 10/24/

(based on 6.776 setup by Mike Perrott)

Table of Contents

Introduction.......................................................... ............................. 2

Upgrade the Device Models............................................................... 3

Update the Schematic for the Transient Simulation........................... 6

Transient Simulation......................................................................... 9

Analysis........................................................................................... 11

Plot the Transient Output ............................................................ 11

Calculate Delays, Rise Times and Power Consumption................. 12

Parametric Simulation..................................................................... 15

Introduction

In this second tutorial we will build on what we learned in the first tutorial. We will learn more sophisticated modeling techniques and more powerful simulation skills. We will use them to answer the question, “For a given load capacitor and a maximum required rise and fall time what is the minimum power required to meet these specs?”

For this we will find useful models that automatically include the increase in source and drain depletion capacitance with increases in the device size. So we will use a parameterized subcircuit around the mos1 model that we created in the first tutorial.

In order to find the rise time, the fall time and the power per cycle we will run a transient simulation.

In order to answer the optimization question, we will use a parametric simulation as an insightful way to pursue the answer.

  • lds = lds
  • ldd = ldd
  • as = max( lds * w, as)
  • ad = max( ldd * w, ad)
  • ps = max(w + 2 * lds, ps)
  • pd = max(w + 2 * ldd, pd)

nmos6012p (d g s b) nmos6012i

ends

inline subckt pmos6012p (d g s b)

parameters w=6e-6 l=1.5e-6 as=2.7e-

  • ad=2.7e-11 ps=1.5e-5 pd=1.5e-
  • nrs=1.5 nrd=1.5 lds=4.5e-6 ldd=4.5e-

model pmos6012i mos

  • type = p
  • l = l
  • w = w
  • vto = -0.
  • kp = 50e-
  • lambda = 7e-2 * (1.5e-6 / l)
  • phi = 0.
  • gamma=0.
  • tox = 1.5e-
  • cj = 3e-
  • cjsw = 3.5e-
  • pb = 0.
  • lds = lds
  • ldd = ldd
  • as = max( lds * w, as)
  • ad = max( ldd * w, ad)
  • ps = max(w + 2 * lds, ps)
  • pd = max(w + 2 * ldd, pd)

pmos6012p (d g s b) pmos6012i

ends

If you have changed the name of the model file, then you need to change the location in ADE as well.

Courtesy of Cadence Design Systems, Inc. Used with permission.

  1. Change the load capacitance to 500f.
  2. Check and Save (X).
  1. Run the simulation by clicking on the green light.

Courtesy of Cadence Design Systems, Inc. Used with permission.

Analysis

Plot the Transient Output

In this section we will plot the transient outputs, show a quick way to measure time differences in the waveform window and calculate rise time, delay and power consumed.

First we plot.

  1. Click ADE->Results->Direct Plot->Transient Signal. Select the output and the input and press Esc.
  2. We can use cursors to get quick estimates of delays in transient plots. Zoom in on any edge using the right mouse button or the zoom menu. Press (a) and left click near 2.5 V on the input waveform. Press (b) and left click near 2.5V on the output waveform. Notice that in the bottom of the waveform window it reports the cursor position of both cursors and their difference, as shown below.

Courtesy of Cadence Design Systems, Inc. Used with permission.

initial value to 90% of the difference above the initial value. This avoids counting long tails as part of the rise time.

d) The final formula should look like. riseTime(clip(VT("/output"),4.5u,5u),0,nil,5,nil,10,90) e) Add this to your ADE outputs window. Plot it or evaluate the buffer (which will consume the formula, so remember to push it onto the stack) to see the value. f) Do the same for fall time.

  1. Now we will calculate the delay through the inverter. We will calculate the delay from the mid point of the input waveform to the midpoint of the output waveform. a) Click on vt. Then in the schematic window select the output node and then the input node, in that order. b) Use SpecialFunctions->delay set as follows and then click OK. This computes the delay from the fifth edge rising past 2.5V of the first waveform to the fifth edge falling past 2.5V of the second waveform.

c) The expression in the window should be: delay(VT("/input"),2.5,5,"rising",VT("/output"),2.5,5,"falling") d) Add this to your ADE->outputs as falldelay. e) Compute the risedelay and add it to your ADE->outputs.

  1. Finally, we will calculate the power consumed by the circuit. Since the entire circuit in the test_inverter schematic is part of the device under test(DUT) we can say that all of the current from our 5V vdc is power consumed by the DUT. We will measure that power over one cycle We are intentionally ignoring the power supplied by the input supply to the gate of the inverter. a) Select the current out of the power supply. In the calculator click it and select

Courtesy of Cadence Design Systems, Inc. Used with permission.

Courtesy of Cadence Design Systems, Inc. Used with permission.

the red dot on the positive terminal of vdc symbol in the schematic. This will write IT(“/V0/PLUS”) in your calculator, if V0 is the name of your supply. b) Calculate the instantaneous power. The instantaneous power will be the current leaving the supply times the voltage or -IT("/V0/PLUS")VT("/vdd!"). You can plot this if you want. c) Now calculate the average power consumed per period by integrating over one cycle and dividing by the duration. Use SpecialFunction->integ. Start at 4.5u and end at 5.5u. Divide by 1u. The formula in the calculator window will look like: integ(-IT("/V0/PLUS")VT("/vdd!"),4.5u,5.5u)/1u d) Add this to your outputs as avepow.

  1. Now go to ADE->Results->Plot Outputs->Expressions to evaluate all of the equations that you added to the ADE otuputs window.

Courtesy of Cadence Design Systems, Inc. Used with permission.

  1. Setup the parametric simulation to sweep wn from 3u to 99u in 2u steps. Click on ADE->Tools->Parametric Analysis. Fill out the window with variable=wn, from=3u, to=99u, step control = linear steps and step size=2u.
  2. Open a new Waveform window, because parametric analysis will plot as soon as it completes and overwrite any plot window that you may have open. ADE->Tools-

    Waveform.

  3. Start the parametric analysis. Parametric->Analysis->Start.
  4. Once it plots change the axis so that both the rise and fall time are on the same axis. Curves->Edit. Then select falltime and change the axis to match risetime.
  5. Now by inspection answer the questions. What is the minimum power and minimum device width required to yield rise and fall times below 1/0.5/0.1 ns given a 500 fF load?

Courtesy of Cadence Design Systems, Inc. Used with permission.

As you can see parametric analysis can allow you to explore 1, 2, 3 or more dimensional slices through your design space, if you can imagine a way to tie a variable to some portion of the design space.

More Play time.

Courtesy of Cadence Design Systems, Inc. Used with permission.