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Lecture on :-ARITHMATIC OPERATIONS

INTRODUCTION Arithmetic Instructions in digital computers manipulate data toproduce results necessary for the of activity solution ofcomputational problems. These instructions perform arithmeticcalculations and are responsible for the bulk of activity involved inprocessing data in a computer. The four basic arithmaticoperations are addition,subtracton,multiplication,division. Fromthese basic operations, it is possible to formulate other arithmaticfunctions and solve scientific problems by means of numericalanalysis methods. An arithmetic processor is the part of a processor unit that execute arithmatic operations.

“The solution to any problem that isstated by a finite number of welldefined procedural steps is calledalgorithm. ”

The fourbasic arithmetic operations are

• ADDITION• SUBTRACTION• MULTIPLICATION• DIVISION

Most computer use the signed 2’s compliment

representation when performing arithmeticoperations with integers. For floating pointoperations , most computers use the signedmagnitude representation.

ADDITION AND SUBTRACTION WITHSIGNED MAGNITUDE DATA

The representation of numbers in signed magnitude is

familer because it is used in everyday arithmeticcalculations. the procedure for adding or subtracting tosigned binary numbers with paper and pencil is simple andstraight forword. a review of this procedure will be helpfulfor deriving the hardware algorithm.

We designate the magnitude of two numbers by

A and B. When the signed numbers added and subtracted, We find that there are eight different conditions toconcider , depending on the sign of the numbers and theoperations performed. This conditions are listed in thefirst coloum of table. The others coloum in the table showthe actual operations to perform with the magnitude ofnumbers.

Eight Conditions for Signed-MagnitudeAddition/Subtraction^ Operation

ADDMagnitu

des

SUBTRACT Magnitudes

A > B

A < B

A = B

(+A) + (+B)

+ (A + B)

(+A) + (-B)

+ (A – B )

- (B – A )

+ (A – B )

(-A) + (+B)

- (A – B )

+ (B – A )

+ (A – B )

(-A) + (-B)

- ( A + B)

(+A) - (+B)

+ (A – B )

- (B – A )

+ (A – B )

(+A) - (-B)

+ (A + B)

(-A) - (+B)

- ( A + B)

(-A) - (-B)

- (A – B )

+ (B – A )

+ (A – B )

Examples Example of adding two

magnitudes when theresult is the sign ofboth operands:

+

0 011

+ +

0 010

+

0 101

Example of adding two

magnitudes when theresult is the sign of thelarger magnitude: Example of adding two

magnitudes when theresult is the sign of thelarger magnitude:

- +2)

- 1

- +2)

- 1

HARDWARE IMPLEMENTATION

• To implement the two arithmetic operation with hardware , it is

first necessary that the two numbers be stored in registers. Let Aand b to registers that hold the magnitude of the numbers , andAs and Bs be two flip – flop that hold the corresponding sings .the result of the operation may be transferred to a third registers :however , a saving Is achived if the result is transferred Into A andAs. Thus A and As together form and accumulator registers .Consider now the hardware implementation of the algorithmabove. first, a parallel – adder is needed to perform themirooperation A + B. second , comparator circuit is needed toestablish if A>B,

X=B,

A<B. Third , two parallel-subtractor

needed to perform the microoperations A – B and B – A. Thesign relationship can be determined from an excellucive and ORgate with As and Bs as inputs. This procedure requires amagnitude comparator , addeFirst , we know that

require less r and two subtractor. however a different

procedure can be less equipment. foundFirst we know thatsubtraction can be accomplished by mean of complimentand add. Second thee result of a compresion can bedetermined for the end carry after the subtraction. Carefullinvestigation of alternatives reveals that the use of 2’scompliment for subtraction and compression is an efficentprocedure that require only an adder and a complementer.Fig. show a block diagram of hardware for implementingthe addition and subtraction operation, It consist ofregisters A and B sign flip – flops As and Bs. Subtraction isdone by adding A to the 2,s complement of B

The output carry is transferred to flip-flop E , where it

can be checked to determined the relative magnitude of twonumbers.

The add overflow flip-flop AVF hold the overflow bit when

A and B are added. The A register provide other micro-operation that may be needed when we Specify thesequence of steps in algorithm. The addition of A + B isdone through the parallel adder. The S (sum) of adder isapplied to input of A register. The complimenterprovides an output of B or compliment of B dependingon the state of mode control M. The complimenterconsist of Excellusve – OR gate and the parallel adderconsist of full-adder circuit as shown in figure. The Msignal is also applied to the input carry is 0. and theoutput of the adder is equal to sum A+B. When M = 1,The 1’s complement of B is appilied to the adder , theinput carry is 1 , and output S=A+b+1. this is equal to Aplus the 2’s ompliment of b , which is equelevent to thesubtraction , A – B.

Hardware algorithm

The two signs As and Bs are compared by an exclusive –OR

gate. If the output of the gate is 0,the signs are identical; ifit is 1 ,the signs are different. For an add operation,identical signs dictate that magnitudes be added. For asubtract operation, different s detcates that themagnitudes be added. The magnitudes are added with amicrooperation igns EA

A+B where EA is a register that

combines E and A. The carry in E after the additionconstitutes an overflow if it is equal to1. The value of E istransferred into the add-overflow flip –flop AVF.The twomagnitudes are subtracted if the signs are different for anadd operation or identical for a subtract operation. Themagnitudes are subtracted by adding A to operation oridentical for a subtract operation. The magnitudes aresubtracted by adding a to the 2’s complement of B

ADDITION AND SUBTRACTION WITHSIGNED 2’S COMPLEMENT DATA^ The left most bit of a binary number presents sign

bit : 0 for +ve and 1 for –ve. If the sign bit is1,the entire number is represented in 2’scompliment form thus, + 33 is represented by00100001 and -33 by 11011111which is 2’scompliment of 00100001 and vice versa.

The addition of two number in signed-2,s

compliment from consist of adding the numbers with thesign bit treated the other bits of the numbers. A carry – out ofthe sign –bit position is discarded .The consist of first takingthe 2’scompliment of the subtrahend and then adding it to theminuend. When two numbers ofn degits each are added andthe sum occupies n+1 digits, we say that an overflow can bededicated by inspecting the last two carries out of theaddition. when the two carries are applied to an exclucive- orgate , the out of the addition. When the two carries areapplied to an exclusive - Or gate , overflow is detected whenthe output of the gate is equal to 1. The register configurationfor the hardware implementation is shown in figure. This isthe same configuration as in fig except that the sign bits arenot seprated. From the rest of the registrators. We name theA register AC (accumulator) and the B register BR.